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    Fluid viscosity control during wafer bonding
    15.
    发明授权
    Fluid viscosity control during wafer bonding 有权

    公开(公告)号：US11056356B1

    公开(公告)日：2021-07-06

    申请号：US16112440

    申请日：2018-08-24

    Applicant: Intel Corporation

    Inventor： Brennen K. Mueller ,  Daniel Pantuso ,  Mauro J. Kobrinsky ,  Chytra Pawashe ,  Myra McDonnell

    IPC: B29C65/00 ,  H01L21/67 ,  H01L21/50 ,  H01L21/673 ,  H01L21/603 ,  B29C65/02 ,  B29C65/78

    Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.

    Detection of known workload patterns
    19.
    发明授权
    Detection of known workload patterns 有权

    公开(公告)号：US11036275B2

    公开(公告)日：2021-06-15

    申请号：US16369643

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Shravan Kumar Belagal Math ,  Noor Mubeen ,  Harinarayanan Seshadri

    IPC: G06F1/00 ,  G06F1/324 ,  G06N20/00 ,  G06F17/16 ,  G06F1/3203

    Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

    Low noise bandgap reference apparatus
    20.
    发明授权
    Low noise bandgap reference apparatus 有权

    公开(公告)号：US11029718B2

    公开(公告)日：2021-06-08

    申请号：US15721521

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Matthias Eberlein

    IPC: G05F3/30 ,  G05F3/22 ,  G05F3/26

    Abstract: An apparatus is provided which includes: a first supply node; a second supply node; a first transistor coupled to the first supply node, the first transistor is to provide a first current which is complementary to absolute temperature (CTAT); a second transistor coupled to the first supply node, the second transistor is to provide a second current which is proportional to absolute temperature (PTAT); a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents.

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