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    Advanced processor with system on a chip interconnect technology
    11.
    发明授权
    Advanced processor with system on a chip interconnect technology 失效
    先进的处理器，采用系统芯片互连技术

    公开(公告)号：US07334086B2

    公开(公告)日：2008-02-19

    申请号：US10898008

    申请日：2004-07-23

    Applicant: David T. Hass ,  Abbas Rashid

    Inventor： David T. Hass ,  Abbas Rashid

    IPC: G06F12/00 ,  G06F15/173

    CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    Weighted instruction count scheduling
    14.
    发明授权
    Weighted instruction count scheduling 有权
    加权指令计数调度

    公开(公告)号：US09069564B1

    公开(公告)日：2015-06-30

    申请号：US13396007

    申请日：2012-02-14

    Applicant: Abbas Rashid ,  David T. Hass

    Inventor： Abbas Rashid ,  David T. Hass

    IPC: G06F9/38

    CPC classification number: G06F9/3851 ,  G06F9/3802

    Abstract: A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.

    Abstract translation: 提供了一种用于在多线程系统中执行有效和有效的调度的方法和系统。 提供了调度的动态控制，其中可以为多线程系统中的一些或所有线程分配优先级权重。 采用优先级权重来控制调度器对线程和线程指令的优先级。 每个线程的指令计数与优先权重组合使用，以确定指令被取出并分配给执行单元进行处理的优先次序顺序。

    Advanced processor with mechanism for fast packet queuing operations
    16.
    发明授权
    Advanced processor with mechanism for fast packet queuing operations 有权
    具有快速数据包排队操作机制的高级处理器

    公开(公告)号：US07924828B2

    公开(公告)日：2011-04-12

    申请号：US10930455

    申请日：2004-08-31

    Applicant: David T. Hass ,  Abbas Rashid

    Inventor： David T. Hass ,  Abbas Rashid

    IPC: H04L12/56

    CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    Cross-bar switch having bandwidth allocation
    18.
    发明授权
    Cross-bar switch having bandwidth allocation 有权
    交叉开关具有带宽分配

    公开(公告)号：US07733905B2

    公开(公告)日：2010-06-08

    申请号：US11670253

    申请日：2007-02-01

    Applicant: Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers ,  Fred Gruner

    Inventor： Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers ,  Fred Gruner

    IPC: H04J3/16

    CPC classification number: H04L49/102 ,  H04L12/42 ,  H04L41/0896 ,  H04L49/101 ,  H04L49/201 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3018

    Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.

    Abstract translation: 交叉开关包括用于接收数据分组的一组输入端口和用于将接收到的分组发送到识别的目标的一组接收端口。 一组数据环将输入端口耦合到接收端口。 每个宿端口利用该组数据环同时接受针对同一目的地的多个数据包 - 创建非阻塞交叉条交换机。 Sink端口还能够支持多个目标 - 为具有隐式组播功能的交叉条交换机提供支持。

    ADVANCED PROCESSOR WITH FAST MESSAGING NETWORK TECHNOLOGY
    19.
    发明申请
    ADVANCED PROCESSOR WITH FAST MESSAGING NETWORK TECHNOLOGY 有权
    具有快速消息传递技术的高级处理器

    公开(公告)号：US20100042785A1

    公开(公告)日：2010-02-18

    申请号：US12582622

    申请日：2009-10-20

    Applicant: David T. Hass ,  Abbas Rashid

    Inventor： David T. Hass ,  Abbas Rashid

    IPC: G06F15/76 ,  G06F12/08 ,  G06F9/02

    CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    ADVANCED PROCESSOR WITH SYSTEM ON A CHIP INTERCONNECT TECHNOLOGY
    20.
    发明申请
    ADVANCED PROCESSOR WITH SYSTEM ON A CHIP INTERCONNECT TECHNOLOGY 失效
    具有芯片互连技术系统的先进处理器

    公开(公告)号：US20080126709A1

    公开(公告)日：2008-05-29

    申请号：US11961884

    申请日：2007-12-20

    Applicant: David T. Hass ,  Abbas Rashid

    Inventor： David T. Hass ,  Abbas Rashid

    IPC: G06F12/08

    CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

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