公开(公告)号：US08510569B2

公开(公告)日：2013-08-13

申请号：US12639616

申请日：2009-12-16

Applicant: Ned Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

Inventor： Ned Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC: G06F9/30 ,  G06F21/22

CPC classification number: G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

Abstract: In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

公开(公告)号：US08431048B2

公开(公告)日：2013-04-30

申请号：US12842200

申请日：2010-07-23

Applicant: Joseph Kuczynski ,  Arvind Kumar Sinha ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil

Inventor： Joseph Kuczynski ,  Arvind Kumar Sinha ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil

IPC: H05K7/20

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/15 ,  C01B32/20 ,  H01L23/373 ,  H01L23/3733 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The exemplary embodiments of the present invention provide a method and system for aligning graphite nanofibers in a thermal interface material to enhance the thermal interface material performance. The method includes preparing the graphite nanofibers in a herringbone configuration, and dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The method further includes applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. The system includes the graphite nanofibers configured in a herringbone configuration and a means for dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The system further includes a means for applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material.

Abstract translation: 本发明的示例性实施例提供了一种用于在石墨纳米纤维中对准热界面材料以提高热界面材料性能的方法和系统。 该方法包括以人字形配置制备石墨纳米纤维，并将石英纳米纤维以人字形构型分散到热界面材料中。 该方法还包括施加足够强度的磁场以使石墨纳米纤维在热界面材料中对准。 该系统包括以人字形配置的石墨纳米纤维和用于将人字形配置中的石墨纳米纤维分散到热界面材料中的装置。 该系统还包括用于施加足够强度的磁场以对准热界面材料中的石墨纳米纤维的装置。

公开(公告)号：US20130073175A1

公开(公告)日：2013-03-21

申请号：US13234881

申请日：2011-09-16

Applicant: Arijit BANERJEE ,  Ajith Kuttainnair KUMAR ,  Arvind Kumar TIWARI ,  Rupam MUKHERJEE ,  Somakumar RAMACHANDRAPANICKER ,  Paul Lloyd FLYNN ,  Boyanapally SRILATHA

Inventor： Arijit BANERJEE ,  Ajith Kuttainnair KUMAR ,  Arvind Kumar TIWARI ,  Rupam MUKHERJEE ,  Somakumar RAMACHANDRAPANICKER ,  Paul Lloyd FLYNN ,  Boyanapally SRILATHA

IPC: G01M15/04 ,  G01M15/05

CPC classification number: F02D29/06 ,  B60K6/46 ,  B60W20/50 ,  B60W2030/206 ,  F02D41/0097 ,  F02D41/1498 ,  F02D41/22 ,  F02D41/221 ,  F02D2041/288 ,  F02D2200/1004 ,  F02D2200/1006 ,  F02D2200/101 ,  F02D2200/1012 ,  F02D2250/24 ,  Y02T10/6217

Abstract: Methods and systems are provided for an engine. A condition of the engine may be diagnosed based on information provided by signals from a generator operationally connected to the engine and/or other signals associated with the engine. Different types of degradation may be distinguished based on discerning characteristics within the information. Thus, a degraded engine component may be identified in a manner that reduces service induced delay.

Abstract translation: 为发动机提供了方法和系统。 可以基于由操作地连接到发动机的发电机和/或与发动机相关联的其它信号的信号提供的信息来诊断发动机的状况。 可以基于信息内的辨别特征来区分不同类型的退化。 因此，可以以减少服务引起的延迟的方式来识别劣化的引擎部件。

公开(公告)号：US08299519B2

公开(公告)日：2012-10-30

申请号：US12685335

申请日：2010-01-11

Applicant: Anthony I. Chou ,  Arvind Kumar

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract translation: 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：US20120217585A1

公开(公告)日：2012-08-30

申请号：US13468270

申请日：2012-05-10

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L27/088

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08232151B2

公开(公告)日：2012-07-31

申请号：US13167303

申请日：2011-06-23

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08212322B2

公开(公告)日：2012-07-03

申请号：US12720354

申请日：2010-03-09

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08114895B2

公开(公告)日：2012-02-14

申请号：US11519200

申请日：2006-09-12

Applicant: Arvind Kumar Singla ,  Javed Naim Agrewala ,  Rakesh Mulraj Vohra ,  Ravinder Singh Jolly

Inventor： Arvind Kumar Singla ,  Javed Naim Agrewala ,  Rakesh Mulraj Vohra ,  Ravinder Singh Jolly

IPC: A61K31/44

CPC classification number: C12P17/165

Abstract: The present invention relates to an isolated bioactive molecule Caerulomycin A, derivatives and analogs thereof as effective immunosuppressive agents. The immunosuppressive property of the compound is targeted in particular against the lymphocytes, CD4+ T cells, CD8+ T cells and B cells and in the production of IL-4 and IFN-γ and antibodies. The compound operates through a mechanism by downregulating the expression of activation marker CD28 and upregulating the immunosuppressive marker CTLA-4. Caerulomycin A has previously been isolated from Streptomyces caeruleus and found to have useful antifungal activity. Prior to the present invention however, this compound had not been determined to have immunomodulatory activity.

Abstract translation: 本发明涉及分离的生物活性分子Caerulomycin A，其衍生物和类似物作为有效的免疫抑制剂。 化合物的免疫抑制特性特别针对淋巴细胞，CD4 + T细胞，CD8 + T细胞和B细胞，以及IL-4和IFN-γ和抗体的产生。 化合物通过下调机制通过下调活化标记CD28的表达和上调免疫抑制标记CTLA-4。 Caerulomycin A先前已经从斑马鱼链霉菌中分离出来，发现其具有有用的抗真菌活性。 然而，在本发明之前，尚未确定该化合物具有免疫调节活性。

公开(公告)号：US08030145B2

公开(公告)日：2011-10-04

申请号：US12684225

申请日：2010-01-08

Applicant: Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

Inventor： Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

IPC: H01L21/84

CPC classification number: H01L21/2652 ,  G03F9/7084 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/26553 ,  H01L21/2658 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/78648 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/8013 ,  H01L2224/802 ,  H01L2924/01019 ,  H01L2924/12044 ,  H01L2924/13091

Abstract: A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.

Abstract translation: 完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。 背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。 在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。 全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

公开(公告)号：US20110169064A1

公开(公告)日：2011-07-14

申请号：US12685335

申请日：2010-01-11

Applicant: Anthony I. Chou ,  Arvind Kumar

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L29/94 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract translation: 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。