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    Non-volatile memory systems having at least one pair of memory cells
    11.
    发明授权
    Non-volatile memory systems having at least one pair of memory cells 有权
    具有至少一对存储单元的非易失性存储器系统

    公开(公告)号：US08897076B2

    公开(公告)日：2014-11-25

    申请号：US13548506

    申请日：2012-07-13

    Applicant: Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    Inventor： Bong-Yong Lee ,  Jung-In Han ,  Hae-Bum Lee ,  Sang-Eun Lee ,  Jung-Ro Ahn ,  Kyung-Jun Shin ,  Tae-Hyun Yoon

    IPC: G11C16/28 ,  G11C16/06

    CPC classification number: G11C16/06 ,  G11C16/28

    Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

    Abstract translation: 在非易失性存储器系统中，用于存储数据的多个主存储单元被布置在数据单元阵列中，并且多个参考存储单元被布置在参考单元阵列中。 参考单元阵列包括连接到第一参考存储器单元的第一参考字线和连接到第二参考存储器单元并与第一参考字线交替延伸的第二参考字线，第一和第二参考存储器 单元交替地连接在一行中，并且组合单元具有一对第一和第二参考存储单元，并产生用于处理数据的参考信号。 第一和第二参考存储单元具有不同的单元特性。 无论第一和第二参考存储单元的区别如何，参考信号的稳定性得到改善。

    FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME
    16.
    发明申请
    FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME 有权
    具有选择位线排放板的闪存存储器件及其操作方法

    公开(公告)号：US20110216602A1

    公开(公告)日：2011-09-08

    申请号：US12813050

    申请日：2010-06-10

    Applicant: Euido Kim ,  Bong Yong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    Inventor： Euido Kim ,  Bong Yong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    IPC: G11C16/06

    CPC classification number: G11C16/06

    Abstract: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

    Abstract translation: 提供了一种闪存器件，其可以包括被配置为存储数据的存储器单元，连接到存储单元的局部位线，连接到本地位线的全局位线，连接到本地位线的放电晶体管 全局位线，并且被配置为响应于放电控制信号选择性地将全局位线连接到参考电平;以及放电控制电路，其通过放电控制信号连接到放电晶体管，并且被配置为 在由闪速存储器件执行的擦除验证操作的验证间隔之前的擦除间隔期间，选择性地禁用放电晶体管。

    Semiconductor memory device and method for repairing the same
    17.
    发明申请
    Semiconductor memory device and method for repairing the same 有权
    半导体存储器件及其修复方法

    公开(公告)号：US20080137454A1

    公开(公告)日：2008-06-12

    申请号：US12000208

    申请日：2007-12-11

    Applicant: Bong-Yong Lee ,  Heon-Kyu Lee ,  Kwang-Soo Kim ,  Sang-Youl Kwon

    Inventor： Bong-Yong Lee ,  Heon-Kyu Lee ,  Kwang-Soo Kim ,  Sang-Youl Kwon

    IPC: G11C29/00

    CPC classification number: G11C29/808 ,  G11C29/846

    Abstract: A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.

    Abstract translation: 半导体存储器件包括形成在主单元阵列区域的一侧的主单元阵列区域，第一冗余单元阵列区域和第一虚设单元阵列区域，以及第二冗余单元阵列区域和第二虚设单元阵列 区域，其形成在主单元阵列区域的另一侧。 第一冗余单元阵列区域包括第一冗余位线，并且第一虚设单元阵列区域包括第一虚拟位线。 第二冗余单元阵列区域包括第二冗余位线，并且第二虚设单元阵列区域包括第二虚拟位线。 第一和第二冗余单元阵列区域比第一和第二虚设单元阵列区域更靠近主单元阵列区域设置。

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