公开(公告)号：US07781296B2

公开(公告)日：2010-08-24

申请号：US11570731

申请日：2005-06-07

Applicant: Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

Inventor： Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

IPC: H01L21/20

CPC classification number: H01L28/84 ,  H01L28/90

Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.

Abstract translation: 集成电路（IC）包括至少一个具有金属电极的电容器。 至少一个电极（10或30）由至少表面硅化半球形硅或硅合金形成。 还提供了用硅化金属电极获得这种电容器的制造工艺。

公开(公告)号：US20080278886A1

公开(公告)日：2008-11-13

申请号：US12074267

申请日：2008-02-29

Applicant: Benoit Froment

Inventor： Benoit Froment

IPC: H01G4/30 ,  H01L21/20

CPC classification number: H01L21/32139 ,  H01L28/84

Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighbouring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.

Abstract translation: 公开了电容耦合器件和制造电容耦合器件的方法。 耦合装置可以包括形成电极和至少一个绝缘体的一叠层。 绝缘体可以包括掺杂硅的区域。 该硅可掺杂选自Ce，Cr，Co，Cu，Dy，Er，Eu，Ho，Ir，Li，Lu，Mn，Pr，Rb，Sm，Sr，Tb，Tm，Yb，Y， Ac，Am，Ba，Be，Cd，Gd，Fe，La，Pb，Ni，Ra，Sc，Th，Hf，Tl，Sn，Np，Rh，U，Zn，Ag和Yb相对于浮雕和成型粗糙度 到堆叠中相同级别的相邻区域。 电极和绝缘体在掺杂硅区域之上形成共形层。

公开(公告)号：US20050186701A1

公开(公告)日：2005-08-25

申请号：US10873750

申请日：2004-06-21

Applicant: Benoit Froment ,  Francois Wacquant

Inventor： Benoit Froment ,  Francois Wacquant

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: A semiconductor material is protected against the formation of a metal silicide by forming a layer of a silicon/germanium alloy on the material. The material which is protected belongs to a component of an integrated circuit comprising other components that have to be subjected to a siliciding operation. The method of protection includes depositing a layer of silicon/germanium alloy on the integrated circuit. The layer of silicon/germanium alloy is then removed from the areas to be silicided. A metal is then deposited on the structure and a metal silicide is formed therefrom. The unreacted metal and the metal/ silicon/germanium ternary alloy that may have formed are removed, and the layer of silicon/germanium alloy is removed so as to expose the unsilicided component.

Abstract translation: 通过在材料上形成硅/锗合金层来保护半导体材料免受金属硅化物的形成。 被保护的材料属于集成电路的部件，该集成电路包括必须进行硅化操作的其它部件。 保护方法包括在集成电路上沉积一层硅/锗合金。 然后将硅/锗合金层从要被硅化的区域中取出。 然后在结构上沉积金属，由此形成金属硅化物。 去除可能形成的未反应的金属和金属/硅/锗三元合金，并除去硅/锗合金层，以暴露未被硅化的组分。

公开(公告)号：US20080135827A1

公开(公告)日：2008-06-12

申请号：US11904305

申请日：2007-09-25

Applicant: Benoit Froment ,  Etienne Robilliart

Inventor： Benoit Froment ,  Etienne Robilliart

IPC: H01L29/08

CPC classification number: H01L49/003

Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

Abstract translation: 本发明涉及一种厚度在1至5个原子之间的导电层，绝缘栅极形成在导电层的一部分上。

公开(公告)号：US20070034948A1

公开(公告)日：2007-02-15

申请号：US11458497

申请日：2006-07-19

Applicant: Florian Cacho ,  Benoit Froment

Inventor： Florian Cacho ,  Benoit Froment

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/66507 ,  H01L29/6653

Abstract: An integrated circuit provided with an NMOS transistor includes a metal silicide on source, drain and gate regions and also on at least one portion of the source and drain extension zones The metal silicide portion located on the source and drain extension zones is thinner than the metal silicide portion located on the source and drain regions.

Abstract translation: 设置有NMOS晶体管的集成电路包括源极，漏极和栅极区域上的金属硅化物以及源极和漏极延伸区域的至少一部分。位于源极和漏极延伸区域上的金属硅化物部分比金属 位于源区和漏区的硅化物部分。

公开(公告)号：US20060172492A1

公开(公告)日：2006-08-03

申请号：US11329358

申请日：2006-01-10

Applicant: Benoit Froment ,  Delphine Aime

Inventor： Benoit Froment ,  Delphine Aime

IPC: H01L21/336

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L21/32105 ,  H01L29/4975 ,  H01L29/66545

Abstract: An MOS transistor with a fully silicided gate is produced by forming a silicide compound in the gate separately and independently of silicide portions located in source and drain zones of the transistor. To this end, the silicide portions of the source and drain zones are covered by substantially impermeable coatings. The coatings prevent the silicide portions of the source and drain zones from increasing in volume during separate and independent formation of the gate silicide compound. The silicide gate may thus be thicker than the silicide portions of the source and drain zones.

公开(公告)号：US20050208765A1

公开(公告)日：2005-09-22

申请号：US10871542

申请日：2004-06-18

Applicant: Francois Wacquant ,  Christophe Regnier ,  Benoit Froment ,  Damien Lenoble ,  Rebha El Farhane

Inventor： Francois Wacquant ,  Christophe Regnier ,  Benoit Froment ,  Damien Lenoble ,  Rebha El Farhane

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/94 ,  H01L21/4763 ,  H01L31/119

CPC classification number: H01L21/26506 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/665

Abstract: A process for forming a silicide on top of at least one silicon portion on the surface of a semiconductor wafer, comprising the following steps: a) implanting, at a defined depth in the silicon portion, through a dielectric layer, of ions that have the property of limiting the silicidation of metals; b) performing heat treatment; c) depositing a metal layer, the metal being capable of forming a silicide by thermal reaction with the silicon; d) performing rapid thermal processing suitable for siliciding the metal deposited at step c); and e) removing the metal that has not reacted to the thermal processing of step d). Advantageously, the thickness of the silicide layer created at step d) is controlled by a suitable choice of the depth of the implantation carried out in step a).

Abstract translation: 一种用于在半导体晶片的表面上的至少一个硅部分的顶部上形成硅化物的工艺，其包括以下步骤：a）在硅部分的限定深度处，通过电介质层注入离子，所述离子具有 限制金属硅化物的性质; b）进行热处理; c）沉积金属层，所述金属能够通过与硅的热反应形成硅化物; d）执行适于硅化沉积在步骤c）的金属的快速热处理; 以及e）除去未与步骤d）的热处理反应的金属。 有利地，通过在步骤a）中进行的注入深度的合适选择来控制在步骤d）产生的硅化物层的厚度。