公开(公告)号：US20050186701A1

公开(公告)日：2005-08-25

申请号：US10873750

申请日：2004-06-21

Applicant: Benoit Froment ,  Francois Wacquant

Inventor： Benoit Froment ,  Francois Wacquant

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: A semiconductor material is protected against the formation of a metal silicide by forming a layer of a silicon/germanium alloy on the material. The material which is protected belongs to a component of an integrated circuit comprising other components that have to be subjected to a siliciding operation. The method of protection includes depositing a layer of silicon/germanium alloy on the integrated circuit. The layer of silicon/germanium alloy is then removed from the areas to be silicided. A metal is then deposited on the structure and a metal silicide is formed therefrom. The unreacted metal and the metal/ silicon/germanium ternary alloy that may have formed are removed, and the layer of silicon/germanium alloy is removed so as to expose the unsilicided component.

Abstract translation: 通过在材料上形成硅/锗合金层来保护半导体材料免受金属硅化物的形成。 被保护的材料属于集成电路的部件，该集成电路包括必须进行硅化操作的其它部件。 保护方法包括在集成电路上沉积一层硅/锗合金。 然后将硅/锗合金层从要被硅化的区域中取出。 然后在结构上沉积金属，由此形成金属硅化物。 去除可能形成的未反应的金属和金属/硅/锗三元合金，并除去硅/锗合金层，以暴露未被硅化的组分。

公开(公告)号：US20050208765A1

公开(公告)日：2005-09-22

申请号：US10871542

申请日：2004-06-18

Applicant: Francois Wacquant ,  Christophe Regnier ,  Benoit Froment ,  Damien Lenoble ,  Rebha El Farhane

Inventor： Francois Wacquant ,  Christophe Regnier ,  Benoit Froment ,  Damien Lenoble ,  Rebha El Farhane

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/94 ,  H01L21/4763 ,  H01L31/119

CPC classification number: H01L21/26506 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/665

Abstract: A process for forming a silicide on top of at least one silicon portion on the surface of a semiconductor wafer, comprising the following steps: a) implanting, at a defined depth in the silicon portion, through a dielectric layer, of ions that have the property of limiting the silicidation of metals; b) performing heat treatment; c) depositing a metal layer, the metal being capable of forming a silicide by thermal reaction with the silicon; d) performing rapid thermal processing suitable for siliciding the metal deposited at step c); and e) removing the metal that has not reacted to the thermal processing of step d). Advantageously, the thickness of the silicide layer created at step d) is controlled by a suitable choice of the depth of the implantation carried out in step a).

Abstract translation: 一种用于在半导体晶片的表面上的至少一个硅部分的顶部上形成硅化物的工艺，其包括以下步骤：a）在硅部分的限定深度处，通过电介质层注入离子，所述离子具有 限制金属硅化物的性质; b）进行热处理; c）沉积金属层，所述金属能够通过与硅的热反应形成硅化物; d）执行适于硅化沉积在步骤c）的金属的快速热处理; 以及e）除去未与步骤d）的热处理反应的金属。 有利地，通过在步骤a）中进行的注入深度的合适选择来控制在步骤d）产生的硅化物层的厚度。

公开(公告)号：US08975682B2

公开(公告)日：2015-03-10

申请号：US12861256

申请日：2010-08-23

Applicant: Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

Inventor： Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

IPC: H01L29/94 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L28/84 ,  H01L28/90

Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.

Abstract translation: 集成电路（IC）包括至少一个具有金属电极的电容器。 至少一个电极（10或30）由至少表面硅化半球形硅或硅合金形成。 还提供了用硅化金属电极获得这种电容器的制造工艺。

公开(公告)号：US20110095375A1

公开(公告)日：2011-04-28

申请号：US12984465

申请日：2011-01-04

Applicant: Benoit Froment ,  Etienne Robilliart

Inventor： Benoit Froment ,  Etienne Robilliart

IPC: H01L27/088

CPC classification number: H01L49/003

Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

Abstract translation: 本发明涉及一种厚度在1至5个原子之间的导电层，绝缘栅极形成在导电层的一部分上。

公开(公告)号：US20080185681A1

公开(公告)日：2008-08-07

申请号：US11570731

申请日：2005-06-07

Applicant: Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

Inventor： Aomar Halimaoui ,  Rebha El Farhane ,  Benoit Froment

IPC: H01L21/20 ,  H01L29/00

CPC classification number: H01L28/84 ,  H01L28/90

Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.

Abstract translation: 集成电路（IC）包括至少一个具有金属电极的电容器。 至少一个电极（10或30）由至少表面硅化半球形硅或硅合金形成。 还提供了用硅化金属电极获得这种电容器的制造工艺。

公开(公告)号：US20070099408A1

公开(公告)日：2007-05-03

申请号：US11592398

申请日：2006-11-02

Applicant: Delphine Aime ,  Benoit Froment

Inventor： Delphine Aime ,  Benoit Froment

IPC: H01L21/4763 ,  H01L21/3205

CPC classification number: H01L29/66507 ,  H01L21/26513 ,  H01L21/28097

Abstract: An embodiment of a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device to transform all or part of the silicon areas into silicide areas, whereby the silicide areas formed at the level of the first silicon areas are thinner than the silicide areas formed at the level of the second silicon areas.

Abstract translation: 一种用于在包括第一和第二硅区域的器件中形成不同厚度的硅化物区域的方法的实施例，包括以下步骤：在第一硅区域的上部注入锑或铝; 用金属材料覆盖硅区域; 并且加热该器件以将全部或部分硅区域转化为硅化物区域，由此形成在第一硅区域的层面处的硅化物区域比形成在第二硅片区域的硅化物区域薄。

公开(公告)号：US06627093B1

公开(公告)日：2003-09-30

申请号：US09673203

申请日：2000-10-12

Applicant: Benoit Froment ,  Phillipe Gayet ,  Erik Van Der Vegt

Inventor： Benoit Froment ,  Phillipe Gayet ,  Erik Van Der Vegt

IPC: H01L2100

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

Abstract translation: 至少一层电介质材料3沉积在被封装层2覆盖的铜轨道1上。在未来垂直连接位置的电介质材料层中蚀刻腔体6。 在所述空腔中沉积至少一个保护层以阻止铜7的扩散。对空腔6底部的保护层7进行各向异性蚀刻处理，并且还对封装层2进行蚀刻，之后空腔为 充满铜。 在蚀刻封装层期间粉碎的铜颗粒不会污染电介质材料3。

公开(公告)号：US08354725B2

公开(公告)日：2013-01-15

申请号：US12984465

申请日：2011-01-04

Applicant: Benoit Froment ,  Etienne Robilliart

Inventor： Benoit Froment ,  Etienne Robilliart

IPC: H01L21/70 ,  H01L27/118

CPC classification number: H01L49/003

Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

Abstract translation: 本发明涉及一种厚度在1至5个原子之间的导电层，绝缘栅极形成在导电层的一部分上。

公开(公告)号：US07622387B2

公开(公告)日：2009-11-24

申请号：US12065256

申请日：2005-08-29

Applicant: Vidya Kaushik ,  Benoit Froment

Inventor： Vidya Kaushik ,  Benoit Froment

IPC: H01L21/44

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665

Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.

Abstract translation: 通过在其间沉积至少两层硅的金属层，由硅和金属形成完全硅化的栅电极。 硅层之一可以是非晶硅，而另一个硅层可以是多晶硅。 金属层和栅极电介质之间的硅可以沉积成具有不同结晶度的两层。 该过程使得能够在由该硅化过程产生的硅化物的相位上进行更大的控制。

公开(公告)号：US20080197498A1

公开(公告)日：2008-08-21

申请号：US12065256

申请日：2005-08-29

Applicant: Vidya Kaushik ,  Benoit Froment

Inventor： Vidya Kaushik ,  Benoit Froment

IPC: H01L29/49 ,  H01L21/283

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665

Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.

Abstract translation: 通过在其间沉积至少两层硅的金属层，由硅和金属形成完全硅化的栅电极。 硅层之一可以是非晶硅，而另一个硅层可以是多晶硅。 金属层和栅极电介质之间的硅可以沉积成具有不同结晶度的两层。 该过程使得能够在由该硅化过程产生的硅化物的相位上进行更大的控制。