公开(公告)号：US06656822B2

公开(公告)日：2003-12-02

申请号：US09344918

申请日：1999-06-28

Applicant: Brian S. Doyle ,  Brian Roberds ,  Sandy S. Lee ,  Quat Vu

Inventor： Brian S. Doyle ,  Brian Roberds ,  Sandy S. Lee ,  Quat Vu

IPC: H01L21265

CPC classification number: H01L23/5329 ,  H01L21/31155 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.

Abstract translation: 降低介电层的介电常数的方法。 首先，在第一导电层上形成电介质层。 然后将物质注入电介质层。

公开(公告)号：US06489655B2

公开(公告)日：2002-12-03

申请号：US09782540

申请日：2001-02-12

Applicant: Brian S. Doyle ,  Brian Roberds ,  Rafael Rios

Inventor： Brian S. Doyle ,  Brian Roberds ,  Rafael Rios

IPC: H01L2701

CPC classification number: H01L29/78621 ,  H01L29/78606 ,  H01L29/78696

Abstract: An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.

Abstract translation: 对集成电路及其制作方法进行说明。 集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。 在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。 集成电路还包括形成在膜上的栅电极。 在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。 掺杂区域具有与体带相隔至少约500埃的交点。

公开(公告)号：US06399973B1

公开(公告)日：2002-06-04

申请号：US09752335

申请日：2000-12-29

Applicant: Brian Roberds

Inventor： Brian Roberds

IPC: H01L2976

CPC classification number: H01L29/66636 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0653

Abstract: A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.

Abstract translation: 通过形成与源极相邻的绝缘层和与漏极相邻的绝缘层来分离MOS晶体管中的源极和漏极的方法以及由该方法制造的装置。

公开(公告)号：US06815310B2

公开(公告)日：2004-11-09

申请号：US10366771

申请日：2003-02-14

Applicant: Brian Roberds ,  Brian S. Doyle

Inventor： Brian Roberds ,  Brian S. Doyle

IPC: H01L2176

CPC classification number: H01L29/66916 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/802

Abstract: A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

公开(公告)号：US06563152B2

公开(公告)日：2003-05-13

申请号：US09752333

申请日：2000-12-29

Applicant: Brian Roberds ,  Brian S. Doyle

Inventor： Brian Roberds ,  Brian S. Doyle

IPC: H01L2976

CPC classification number: H01L29/66916 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/802

Abstract: A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

公开(公告)号：US06362082B1

公开(公告)日：2002-03-26

申请号：US09342030

申请日：1999-06-28

Applicant: Brian S. Doyle ,  Brian Roberds

Inventor： Brian S. Doyle ,  Brian Roberds

IPC: H01L21265

CPC classification number: H01L29/0649 ,  H01L21/26506 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/7842

Abstract: A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

公开(公告)号：US20060205178A1

公开(公告)日：2006-09-14

申请号：US11429903

申请日：2006-05-08

Applicant: Brian Doyle ,  Brian Roberds

Inventor： Brian Doyle ,  Brian Roberds

IPC: H01L21/46

CPC classification number: H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664

Abstract: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Abstract translation: 一种将应变硅膜制造到绝缘硅（SOI）晶片上的方法。 一层氧化物沉积在具有第一基底，松弛膜层和第二层应变膜的堆叠结构的晶片上。 SOI晶片具有第二基底基板和氧化膜层的堆叠结构。 SOI晶片连接到晶片并在第一温度下被加热。 这导致在SOI晶片的第二基底衬底上形成二氧化硅（SiO 2/2）悬挂键，将应变膜从一个晶片转移到另一个晶片。

公开(公告)号：US06809017B2

公开(公告)日：2004-10-26

申请号：US10452088

申请日：2003-05-30

Applicant: Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

Inventor： Reza Arghavani ,  Robert Chau ,  Mark Doczy ,  Brian Roberds

IPC: H01L213205

CPC classification number: H01L21/28176 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4925 ,  H01L29/517

Abstract: Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

Abstract translation: 制造半导体器件的方法 半导体器件包括衬底，形成在衬底上的高k栅介质层和沉积在高k栅介质层上的无氢栅电极，其中无氢栅电极是导电的。 该方法包括在衬底上沉积高k栅极电介质层，在栅极电介质层上溅射栅电极并处理栅电极使得栅电极是导电的。

公开(公告)号：US06638835B2

公开(公告)日：2003-10-28

申请号：US10015107

申请日：2001-12-11

Applicant: Brian Roberds ,  Cindy Colinge ,  Brian Doyle

Inventor： Brian Roberds ,  Cindy Colinge ,  Brian Doyle

IPC: H01L21461

CPC classification number: H01L21/76254 ,  Y10S438/977 ,  Y10T428/24355

Abstract: The invention relates to a semiconductor structure that is formed by delaminating a semiconductor substrate and by bonding the top section of the substrate to a transfer substrate. Delaminating is carried out by causing a polymer film to achieve greater adhesion that an embrittlement layer in the semiconductor substrate.

Abstract translation: 本发明涉及一种半导体结构，其通过使半导体衬底分层并将衬底的顶部部分粘合到转移衬底而形成。 通过使聚合物膜实现在半导体衬底中的脆化层的更大的附着力来进行分层。

公开(公告)号：US06518109B2

公开(公告)日：2003-02-11

申请号：US10106153

申请日：2002-03-26

Applicant: Brian Roberds

Inventor： Brian Roberds

IPC: H01L21336

CPC classification number: H01L29/66636 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0653

Abstract: A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.