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公开(公告)号：US20110056735A1
公开(公告)日：2011-03-10
申请号：US12649071
申请日：2009-12-29
Applicant: Byoung Hwa Lee , Dong Seok Park , Young Ghyu Ahn , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa Lee , Dong Seok Park , Young Ghyu Ahn , Sang Soo Park , Min Cheol Park
Abstract: There are provided a multilayer chip capacitor and a circuit board device. The multilayer chip capacitor includes a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity, first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes, and third inner electrodes interposed between the first and second inner electrodes. At least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode. At least one of the third inner electrodes adjacent to the second inner electrode includes a conductive pattern having the same shape as the lead of the second inner electrode and is connected to the second outer electrode.
Abstract translation: 提供了多层片状电容器和电路板装置。 多层片状电容器包括电容器本体，其包括层叠的多个电介质层，形成在电容器本体的外表面上并具有相反极性的第一和第二外部电极，彼此相对的第一和第二内部电极，与电介质 层，并且每个包括电极板形成电容和从电极板延伸的引线，第一内部电极的引线和第二电极的引线分别连接到第一和第二外部电极，第三 介于第一和第二内部电极之间的内部电极。 与第一内部电极相邻的第三内部电极中的至少一个包括具有与第一内部电极的引线相同形状并且连接到第一外部电极的导电图案。 与第二内部电极相邻的第三内部电极中的至少一个包括具有与第二内部电极的引线相同形状并且连接到第二外部电极的导电图案。
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12.发明授权Integrated multilayer chip capacitor module and integrated circuit apparatus having the same 有权集成多层片状电容器模块及其集成电路装置公开(公告)号：US07889479B2
公开(公告)日：2011-02-15
申请号：US12007737
申请日：2008-01-15
Applicant: Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park
Inventor： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park
IPC: H01G4/228
CPC classification number: H01G4/232 , H01G2/06 , H01G4/38 , H01L23/50 , H01L2924/0002 , H01L2924/00
Abstract: An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.
Abstract translation: 一种集成多层片状电容器模块，包括：彼此靠近并且彼此共面布置的多个多层片状电容器; 以及容纳所述多层片状电容器的电容器支架，其中，所述多层片状电容器中的每一者包括长方体电容器主体和形成在所述电容器主体的至少两侧的多个第一外部电极和所述第二外部电极， 的电容器支撑体中的多层片状电容器的相邻电容器通过导电性粘合剂材料彼此电连接。
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13.发明授权Circuit board for mounting multilayer chip capacitor and circuit board apparatus including the multilayer chip capacitor 有权用于安装多层片状电容器的电路板和包括多层片状电容器的电路板装置公开(公告)号：US07684204B2
公开(公告)日：2010-03-23
申请号：US12155583
申请日：2008-06-06
Applicant: Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H05K7/00
CPC classification number: H01L23/50 , H01G4/35 , H01L23/49838 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/113 , H05K2201/0792 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2924/00
Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.
Abstract translation: 一种电路板，包括：具有用于安装具有第一极性的第一和第二外部电极和第二极性的第三外部电极的垂直多层片状电容器的安装区域的基板; 布置在安装区域上的第一至第三焊盘，第一和第二焊盘具有第一极性并且在安装区域上彼此分开设置，第三焊盘具有第二极性并且设置在第一焊盘和第二焊盘之间以连接到 第三外部电极; 至少一个第一通孔，其形成在所述基板中并连接到所述第一焊盘; 至少一个第二通孔，形成在所述衬底中并连接到所述第二衬垫; 以及形成在基板中并连接到第三焊盘的多个第三通孔。 第一通孔相对于第一焊盘的中心线设置成与第三焊盘相邻，第二通孔相对于第二焊盘的中心线设置为与第三焊盘相邻，第一通孔中的一个或多个邻近 相对于第三焊盘的中心线移动到第一通孔，并且第三通孔的其余部分相对于第三焊盘的中心线设置成与第二通孔相邻。
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公开(公告)号：US20100033897A1
公开(公告)日：2010-02-11
申请号：US12340200
申请日：2008-12-19
Applicant: Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H01G4/38
Abstract: There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.
Abstract translation: 提供了一种多层片状电容器，其包括：电容器主体，包括布置在其中的第一和第二电容器单元; 以及第一至第四外部电极，其中所述第一电容器单元包括第一和第二内部电极，并且所述第一电容器单元包括多个电容器元件，每个电容器元件具有反复层叠的一对第一和第二内部电极，所述第二电容器单元包括第三电极单元 和第四内部电极，并且第二电容器单元包括至少一个电容器元件，其具有重复层叠的一对第三和第四内部电极，并且第一电容器单元的电容器元件中的至少一个与其他电容器元件不同 第一电容器单元的第一和第二内部电极的叠层数或谐振频率。
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公开(公告)号：US20090225492A1
公开(公告)日：2009-09-10
申请号：US12248476
申请日：2008-10-09
Applicant: Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H01G4/005
Abstract: A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.
Abstract translation: 多层片状电容器包括电容器主体，其包括多个电介质层的叠层，并且具有第一和第二侧面以及第一和第二端面，多个相反极性的外部电极在第一和第二侧面中的每一个上交替， 以及多个内部电极，每个内部电极包括延伸到电容器主体的外表面并分别连接到外部电极的一个或两个引线。 在堆叠方向上彼此相邻的内部电极的引线之间的水平距离比在电容器主体的同一侧面上彼此相邻的外部电极之间的间距长。
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Patent Agency Ranking
公开(公告)号：US20090213525A1
公开(公告)日：2009-08-27
申请号：US12245865
申请日：2008-10-06
Applicant: Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H01G4/005
Abstract: A multilayer chip capacitor includes a capacitor body including first and second longer side surfaces facing each other and first and second shorter side surfaces facing each other, first and second external electrodes respectively disposed at the first and second longer side surfaces, one or more first internal electrode pairs each including first and second internal electrodes, and one or more second internal electrode pairs each including third and fourth internal electrodes. The first to fourth internal electrodes each have one lead and are sequentially disposed in a stacked direction. The first to fourth internal electrodes have first to fourth leads respectively extending to first to fourth corners or portions adjacent thereto, and alternately connected with the first and second external electrodes. The first internal electrode pair and the second internal electrode pair cause a current to diagonally flow in opposite directions with respect to a long side direction.
Abstract translation: 一种多层片状电容器包括：电容器主体，包括彼此面对的第一和第二较长侧表面;以及彼此面对的第一和第二短边表面，分别设置在第一和第二长边侧表面的第一和第二外部电极， 每个电极对包括第一和第二内部电极，以及一个或多个第二内部电极对，每个包括第三和第四内部电极。 第一至第四内部电极各自具有一个引线并且沿堆叠方向依次布置。 第一至第四内部电极具有分别延伸到第一至第四角部或与其相邻的部分的第一至第四引线，并且与第一和第二外部电极交替连接。 第一内部电极对和第二内部电极对使得电流相对于长边方向在相反的方向上斜向流动。
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17.发明申请公开(公告)号：US20090139757A1
公开(公告)日：2009-06-04
申请号：US12195015
申请日：2008-08-20
Applicant: Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
CPC classification number: H05K1/0231 , H01G4/005 , H01G4/232 , H01G4/385 , H05K2201/09481 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
Abstract: A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.
Abstract translation: 一种多层片状电容器，包括：层叠有多个电介质层的叠层结构的电容器体，具有根据层叠方向配置的第一电容器部和第二电容器部; 形成在电容器主体的侧面的第一至第四外部电极，第一和第三外部电极具有相同的极性，第二和第四外部电极具有与第一外部电极的极性相反的极性; 以及一个或多个连接导线，形成在电容器主体的外表面上，并将第一外电极连接到第三外电极或将第二外电极连接到第四外电极。
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公开(公告)号：US20090086405A1
公开(公告)日：2009-04-02
申请号：US12238688
申请日：2008-09-26
Applicant: Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H01G4/228
Abstract: There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.
Abstract translation: 提供一种能够调谐电容的多层片状电容器，包括：电容器体，层叠多个电介质层; 多个成对的第一和第二内部电极交替布置，同时插入相应的一个电介质层; 以及连接到所述第一和第二内部电极的多对第一和第二外部电极，其中所述第一和第二内部电极包括多个组，每个组包括至少一对所述第一和第二内部电极，以及所述第一和第二内部电极 每个组的第二内部电极分别连接到第一和第二外部电极的不同对，其中第一和第二外部电极对中的相应一个选择性地连接到电力线，使得多层片状电容器具有 至少两个不同的电容。
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公开(公告)号：US20090051474A1
公开(公告)日：2009-02-26
申请号：US12194935
申请日：2008-08-20
Applicant: Byoung Hwa LEE , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
Inventor： Byoung Hwa LEE , Sung Kwon Wi , Hyeog Soo Shin , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC: H01F27/02
CPC classification number: H01F17/0013 , H01F3/14 , H01F17/04
Abstract: There is provided a laminated inductor including: a body where a plurality of magnetic layers are laminated; a coil part formed on the magnetic layers, the coil part including a plurality of conductor patterns and a plurality of conductive vias; first and second external electrodes formed on an outer surface of the body to connect to both ends of the coil part, respectively; and a non-magnetic conductor formed on at least one of the magnetic layers so as to relax magnetic saturation caused by direct current flowing through the coil part. The laminated inductor employs the non-magnetic conductor as a non-magnetic gap to be simplified in a manufacturing process and effectively improved in DC superposition characteristics.
Abstract translation: 提供一种层叠电感器，包括：层叠有多个磁性层的主体; 形成在所述磁性层上的线圈部分，所述线圈部分包括多个导体图案和多个导电通孔; 第一外部电极和第二外部电极分别形成在主体的外表面上以连接到线圈部分的两端; 以及形成在至少一个磁性层上的非磁性导体，以便缓和由直流电流流过线圈部分的磁饱和。 层叠电感器在制造工艺中使用非磁性导体作为非磁性间隙进行简化，并有效地改善了DC叠加特性。
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20.发明申请Integrated multilayer chip capacitor module and integrated circuit apparatus having the same 有权集成多层片状电容器模块及其集成电路装置公开(公告)号：US20080204971A1
公开(公告)日：2008-08-28
申请号：US12007737
申请日：2008-01-15
Applicant: Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park
Inventor： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park
IPC: H01G4/228
CPC classification number: H01G4/232 , H01G2/06 , H01G4/38 , H01L23/50 , H01L2924/0002 , H01L2924/00
Abstract: An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.
Abstract translation: 一种集成多层片状电容器模块，包括：彼此靠近并且彼此共面布置的多个多层片状电容器; 以及容纳所述多层片状电容器的电容器支架，其中，所述多层片状电容器中的每一者包括长方体电容器主体和形成在所述电容器主体的至少两侧的多个第一外部电极和所述第二外部电极， 的电容器支撑体中的多层片状电容器的相邻电容器通过导电性粘合剂材料彼此电连接。
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