公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

Applicant: Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

Inventor： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11543

Abstract: A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

Abstract translation: 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US07125766B2

公开(公告)日：2006-10-24

申请号：US11062546

申请日：2005-02-23

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855

Abstract: A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Abstract translation: 公开了一种形成用于半导体器件的电容器的方法。 根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。 各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽 比通过氧化物层的开口的至少一部分。 因此，模具层用于形成具有比其上部宽的下部的存储电极。

公开(公告)号：US07118926B2

公开(公告)日：2006-10-10

申请号：US10652403

申请日：2003-08-29

Applicant: Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

Inventor： Hong Cho ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee ,  Hye-Jin Jo

IPC: H01L21/00

CPC classification number: H01L21/67253 ,  H01L21/32137 ,  H01L21/67069 ,  H01L22/20

Abstract: A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

Abstract translation: 一种优化干蚀刻工艺调味配方的方法。 该方法包括设置重现性的临界值，主蚀刻配方和初步调味配方。 然后使用干蚀刻室中的初步调味配方蚀刻测试晶片。 接下来，使用主蚀刻配方对干蚀刻室中的至少10个运行晶片执行主蚀刻处理，并且确定每个晶片的终点检测时间。 然后使用确定的终点检测时间确定初始色散和标准偏差。 然后将重现性的临界值与初始色散进行比较。 如果初始分散度等于或小于再现性的临界值，则使用初步调味配方作为调味配方，否则初步调味配方被修改，重复该过程直到确定最佳调味配方。

公开(公告)号：US20060128099A1

公开(公告)日：2006-06-15

申请号：US11260377

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

Abstract translation: 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

公开(公告)号：US20060079076A1

公开(公告)日：2006-04-13

申请号：US11247937

申请日：2005-10-11

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC: H01L21/3205 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/1037 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/76

Abstract: Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

公开(公告)号：US20060024932A1

公开(公告)日：2006-02-02

申请号：US11191488

申请日：2005-07-28

Applicant: Heung-Sik Park ,  Kyeong-Koo Chi ,  Chang-Jin Kang

Inventor： Heung-Sik Park ,  Kyeong-Koo Chi ,  Chang-Jin Kang

IPC: H01L21/425

CPC classification number: H01L21/823842

Abstract: Embodiments of the present invention provide methods of forming a semiconductor device including forming a polysilicon layer on a semiconductor substrate and doping the polysilicon layer with P-type impurities. The semiconductor substrate including the polysilicon layer is annealed and then an upper portion having a first thickness of the annealed polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof.

Abstract translation: 本发明的实施例提供了形成半导体器件的方法，该半导体器件包括在半导体衬底上形成多晶硅层，并用P型杂质掺杂多晶硅层。 包括多晶硅层的半导体衬底被退火，然后去除掺杂有P型杂质的退火多晶硅层的第一厚度的上部。 选择第一厚度以去除在其掺杂和/或退火期间在多晶硅层中形成的缺陷。

公开(公告)号：US20050282363A1

公开(公告)日：2005-12-22

申请号：US11157435

申请日：2005-06-21

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/36 ,  H01L21/469 ,  H01L21/60

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，并且形成硅锗（Si 1-Si） xTi）x牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基底的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US20050245026A1

公开(公告)日：2005-11-03

申请号：US11062546

申请日：2005-02-23

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855

Abstract: A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Abstract translation: 公开了一种形成用于半导体器件的电容器的方法。 根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。 各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽 比通过氧化物层的开口的至少一部分。 因此，模具层用于形成具有比其上部宽的下部的存储电极。

公开(公告)号：US6143654A

公开(公告)日：2000-11-07

申请号：US229337

申请日：1999-01-13

Applicant: Jin-hwan Hahm ,  Chang-jin Kang

Inventor： Jin-hwan Hahm ,  Chang-jin Kang

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/52 ,  H01L21/44

CPC classification number: H01L21/32135 ,  H01L21/32139

Abstract: A capping film having a lower etch rate than a tungsten film is formed thereon and a photoresist layer is formed on the capping film. Preferably, the capping film is a titanium-based layer or an aluminum-based layer. After a photoresist pattern is formed by exposing and developing the photoresist film, the tungsten film is patterned by a dry etch method. During the etching of the tungsten film, the capping film reacts with the etching material to form a polymer which serves as a hard mask for the tungsten film. Preferably, the capping film also has a lower reflectivity at the exposing wavelength for the photoresist than the tungsten film, so the exposure of the photoresist may be controlled. Alternatively, or additionally, an anti-reflective film is provided between the capping film and the photoresist to further reduce the effect of the reflection of the tungsten film. Thus, patterning failures can be prevented. Such a method is particularly advantageous when the tungsten film pattern formed thereby is to be used as a bit line in a semiconductor device, particularly a pattern having a design rule of 0.34 .mu.m or less.

Abstract translation: 在其上形成具有比钨膜蚀刻速率更低的覆盖膜，并且在封盖膜上形成光致抗蚀剂层。 优选地，封盖膜是钛基层或铝基层。 在通过曝光和显影光致抗蚀剂膜形成光致抗蚀剂图案之后，通过干蚀刻方法对钨膜进行图案化。 在钨膜的蚀刻期间，封盖膜与蚀刻材料反应形成用作钨膜的硬掩模的聚合物。 优选地，封盖膜在光致抗蚀剂的曝光波长处还具有比钨膜更低的反射率，因此可以控制光致抗蚀剂的曝光。 或者或另外，在覆盖膜和光致抗蚀剂之间提供抗反射膜，以进一步降低钨膜的反射效果。 因此，可以防止图案化故障。 当由此形成的钨膜图形用作半导体器件中的位线时，特别是设计规则为0.34μm或更小的图案，这种方法是特别有利的。

公开(公告)号：US08941165B2

公开(公告)日：2015-01-27

申请号：US12779300

申请日：2010-05-13

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/314 ,  H01L21/316

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。