公开(公告)号：US06586324B2

公开(公告)日：2003-07-01

申请号：US10057085

申请日：2002-01-25

Applicant: Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

Inventor： Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

IPC: H01L214763

CPC classification number: H01L21/76837 ,  H01L21/76834

Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

Abstract translation: 形成互连的方法。 形成具有图案的氧化物掩模层，覆盖金属层。 将掩模层的图案转移到金属层中以形成开口。 然后，在掩模层，金属层和第一绝缘层上共形地形成氮化硅衬垫。 接下来，通过反应离子蚀刻部分去除氮化硅衬垫和掩模层以留下刻面掩模以减小开口的纵横比，随后除去剩余的氮化硅衬垫。 然后，沉积绝缘层以填充开口。

公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

Applicant: Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract translation: 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US20130045600A1

公开(公告)日：2013-02-21

申请号：US13210172

申请日：2011-08-15

Applicant: Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/308

CPC classification number: H01L29/7854 ,  H01L29/7853

Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

Abstract translation: 提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

Applicant: Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

Inventor： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC: G03F7/00

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract translation: 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06992393B2

公开(公告)日：2006-01-31

申请号：US10708848

申请日：2004-03-29

Applicant: Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract translation: 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

公开(公告)号：US5366079A

公开(公告)日：1994-11-22

申请号：US108249

申请日：1993-08-19

Applicant: Chih-Ching Lin ,  Jiin C. Tai ,  Jane-Hong Huang ,  Ying-Kuang Peng

Inventor： Chih-Ching Lin ,  Jiin C. Tai ,  Jane-Hong Huang ,  Ying-Kuang Peng

IPC: H01L21/673 ,  B65D73/02 ,  B65D85/02 ,  B65D85/42

CPC classification number: H01L21/67369 ,  Y10S206/821

Abstract: The container has an enclosure member and a body member which together enclose a volume to accept wafers for storage, for handling, or for transportation. The body member has a base, and a plurality of spaced upright arcuate members supported on the base that are adapted to encircle wafers stacked on the base. An enclosure member has a circular top wall and a cylindrically shaped wall that is adapted to encompass and enclose the arcuate members. The retainer element has a flat central portion, and a plurality of flexible outwardly extending flaps depending from the central portion. The retainer element fits within the arcuate members of the body member with the end portions of the flaps positioned in the slots between the arcuate members.

Abstract translation: 容器具有封闭构件和主体构件，其一起封闭体积以接收用于存储，处理或运输的晶片。 主体构件具有底座，以及支撑在基座上的多个间隔开的直立弓形构件，其适于环绕堆叠在基座上的晶片。 外壳构件具有圆形顶壁和圆柱形壁，其适于包围和包围弓形构件。 保持器元件具有平坦的中心部分和从中心部分悬垂的多个柔性向外延伸的翼片。 保持器元件装配在主体构件的弓形构件内，翼片的端部位于弓形构件之间的槽中。

公开(公告)号：US08592320B2

公开(公告)日：2013-11-26

申请号：US13210172

申请日：2011-08-15

Applicant: Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/302

CPC classification number: H01L29/7854 ,  H01L29/7853

Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

Abstract translation: 提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

公开(公告)号：US08389402B2

公开(公告)日：2013-03-05

申请号：US13116432

申请日：2011-05-26

Applicant: Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

Inventor： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

IPC: H01L21/4763

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76898

Abstract: A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.

Abstract translation: 在半导体器件中通孔形成的方法包括以下步骤：提供具有限定通孔开口的光致抗蚀剂图案的光致抗蚀剂，其中包含热交联材料的光致抗蚀剂设置在结构层上; 将结构层干蚀刻穿过开口的第一深度; 烘烤热交联材料以减少开口; 并且通过所述减小的开口将所述结构层干蚀刻到第二深度，其中所述第二深度大于所述第一深度。

公开(公告)号：US20120302070A1

公开(公告)日：2012-11-29

申请号：US13116209

申请日：2011-05-26

Applicant: Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

Inventor： Chih Ching Lin ,  Yi Nan Chen ,  Hsien Wen Liu

IPC: H01L21/3065 ,  C23F1/08

CPC classification number: C23F4/00 ,  H01J37/32091 ,  H01J37/32146 ,  H01L21/32136

Abstract: A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl2 gas, BCl3 gas, HBr gas, and the combination thereof; applying a pulse-modulated high-frequency voltage between a pair of electrodes that are provided in the processing container so as to be opposed to each other and to hold the semiconductor substrate, such that the high-frequency voltage is turned on and off to establish a duty ratio; generating a plasma between the pair of electrodes; and etching the semiconductor substrate using the plasma.

Abstract translation: 一种在半导体器件中执行脉冲蚀刻的方法包括以下步骤：提供半导体衬底，其中金属层设置在半导体衬底上，并将硬掩模层覆盖在金属层上; 将半导体衬底引入处理容器中; 向处理容器中引入蚀刻气体，其中将由C，H和F中的至少两个构成的沉积型气体添加到从由Cl 2气体，BCl 3气体，HBr气体组成的组中选择的蚀刻气体中， 的组合 在设置在处理容器中的一对电极之间施加脉冲调制的高频电压以彼此相对并保持半导体衬底，使得高频电压被接通和断开以建立 占空比 在所述一对电极之间产生等离子体; 并使用等离子体蚀刻半导体衬底。

公开(公告)号：US20120283802A1

公开(公告)日：2012-11-08

申请号：US13554238

申请日：2012-07-20

Applicant: Chih-Ching LIN ,  Chyi-Ran LEE

Inventor： Chih-Ching LIN ,  Chyi-Ran LEE

IPC: A61N5/06

CPC classification number: A61N5/0613 ,  A61N2005/0602 ,  A61N2005/066

Abstract: The present invention provides a novel use of far-infrared radiation for improving patency of arteriovenous fistula, decreasing failure of arteriovenous fistula maturation and preventing and/or ameliorating peripheral artery diseases in a subject in need thereof. The radiation has an electromagnetic wave of about 1.5 to 100 μm wavelength, which performs on the subject skin surface for more than 10 minutes.

Abstract translation: 本发明提供远红外辐射的新用途，用于改善动静脉瘘的通畅，减少动静脉瘘成熟的失败，并预防和/或改善有需要的受试者的外周动脉疾病。 辐射具有约1.5至100μm波长的电磁波，其在主体皮肤表面上执行超过10分钟。