Semiconductor diffused resistors with optimized temperature dependence
    11.
    发明授权
    Semiconductor diffused resistors with optimized temperature dependence 失效
    具有优化温度依赖性的半导体扩散电阻

    公开(公告)号:US07038297B2

    公开(公告)日:2006-05-02

    申请号:US10761890

    申请日:2004-01-21

    IPC分类号: H01L29/00

    CPC分类号: H01L29/8605 Y10S257/904

    摘要: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C.Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

    摘要翻译: 离子注入电阻器形成在晶体硅基体的主体中。 电阻器具有与硅衬底不同的导电类型。 电阻层的薄层电阻和温度依赖性由植入物的剂量决定。 温度变化可以在-40℃至+ 85℃的温度范围内优化为小于2%。此外,室温(〜25℃)下的温度变化可以降低到接近零。

    Variable impedance network with coarse and fine controls

    公开(公告)号:US06744244B2

    公开(公告)日:2004-06-01

    申请号:US10114375

    申请日:2002-04-01

    IPC分类号: H02J312

    CPC分类号: H03H7/24 H03G1/0088

    摘要: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

    Adaptive programming method and apparatus for flash memory analog storage
    13.
    发明授权
    Adaptive programming method and apparatus for flash memory analog storage 失效
    闪存模拟存储的自适应编程方法和装置

    公开(公告)号:US06301151B1

    公开(公告)日:2001-10-09

    申请号:US09634180

    申请日:2000-08-09

    IPC分类号: G11C700

    CPC分类号: G11C16/12 G11C27/005

    摘要: Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

    摘要翻译: 闪存模拟存储的自适应编程方法和装置。 本发明的方法是基于先前脉冲的结果每次调节编程脉冲的电压。 将编程值的预期变化与测量的变化进行比较,以及用于在每个编程脉冲之后改善该单元的模型的差异。 该算法是“自适应”的,因为每个脉冲的电压适应于任何单元需要。 如果电池的编程速度太慢,电压会急剧增加,使其更快。 相反,如果结果显示特定的单元格编程速度太快,则下一个电压脉冲仅增加少量(或者如果需要甚至减小)。 由于单元的响应是非线性的,所以使用特殊的模拟电路来计算每个脉冲的最佳电压。 作为一种替代方案,也可以使用数字计算来对单元进行编程。 由于示例性方法的编程速度,一次可以将语音信号采样并存储在闪存中一个单元。 如果需要,可以使用电压以外的可变编程参数。

    Recording and playback integrated system for analog non-volatile flash
memory
    14.
    发明授权
    Recording and playback integrated system for analog non-volatile flash memory 失效
    用于模拟非易失性闪存的记录和回放集成系统

    公开(公告)号:US5959883A

    公开(公告)日:1999-09-28

    申请号:US4798

    申请日:1998-01-09

    摘要: An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.

    摘要翻译: 使用非易失性闪存的模拟录音和播放系统。 闪存单元阵列用于存储模拟信号,并实时检索存储的模拟信号。 多个列驱动器电路耦合到闪存单元的列,用于同时编程和读取。 使用编程算法将模拟信号写入闪存单元的工作范围内,因为工作范围可能由于工艺变化而偏移。 该系统包括三角电路,以提供可调整的初始编程电压,编程步骤,编程电流,读取电流和选择栅极电压。 该系统还包括与主机微控制器连接的串行外设接口(“SPI”)。 主机微控制器可以通过SPI向系统发送多个命令,以实现高效的消息管理。 这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。 该系统利用行和列冗余来提高产量。

    Variable impedance network with coarse and fine controls
    15.
    发明授权
    Variable impedance network with coarse and fine controls 失效
    可变阻抗网络,粗调和精细控制

    公开(公告)号:US06922046B2

    公开(公告)日:2005-07-26

    申请号:US10817220

    申请日:2004-04-02

    IPC分类号: H03G1/00 H03H7/24 H02J3/12

    CPC分类号: H03H7/24 H03G1/0088

    摘要: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

    摘要翻译: 阻抗网络。 网络包括多个阻抗元件,至少一个端子端子和擦拭器端子。 网络还包括第一多个开关元件,其选择性地向至少一个端子端子提供抽头位置,可在多个阻抗元件中的阻抗元件的第一规定增量处选择。 网络还包括第二多个开关元件,其选择性地提供抽头位置到抽头端子,可选择在多个阻抗元件中的阻抗元件的第二规定增量。