公开(公告)号：US06194285B1

公开(公告)日：2001-02-27

申请号：US09412653

申请日：1999-10-04

Applicant: Chung-Te Lin ,  Kong-Bong Thei ,  Carlos H. Diaz

Inventor： Chung-Te Lin ,  Kong-Bong Thei ,  Carlos H. Diaz

IPC: H01L2176

CPC classification number: H01L21/76237

Abstract: A method is disclosed to form a shallow trench isolation (STI) having reduced junction leakage by avoiding undercutting near the shoulder of the trench. This is accomplished by using the pad oxide as a screen oxide and not removing it by wet dip etch as is normally practiced. Instead, an extra layer of low temperature oxide is added through thermal growth, and then the resulting composite is removed together with minimal undercutting at the shoulder corners of the trench. Subsequently, gate oxide is grown thermally to complete the forming of the STI.

Abstract translation: 公开了一种形成浅沟槽隔离（STI）的方法，其通过避免在沟槽的肩部附近的底切而具有减少的结漏电。 这通过使用垫氧化物作为屏幕氧化物而不是通过湿浸蚀刻如通常实践去除而实现的。 相反，通过热生长添加额外的低温氧化物层，然后将所得到的复合物与沟槽的肩角处的最小的底切一起除去。 随后，栅极氧化物热生长以完成STI的形成。

公开(公告)号：US6103581A

公开(公告)日：2000-08-15

申请号：US200552

申请日：1998-11-27

Applicant: Chung-Te Lin ,  Chin-Hsiung Ho ,  Hann-Huei Tsai

Inventor： Chung-Te Lin ,  Chin-Hsiung Ho ,  Hann-Huei Tsai

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method for fabricating shallow trench isolation stricture wherein a surface oxide layer and a polycrystalline silicon buffer layer are formed on a semiconductor body. Openings are formed through the layers and into the body that constitute trenches. A lining oxide layer is formed on the trench and buffer layer surfaces. A thick oxide layer is deposited on the body to fill the trench, and the layer planarized by chemical-mechanical polishing. The exposed portions of the buffer layer are removed and the horizontal surface oxide layer portions removed by anisotropic etching.

Abstract translation: 一种制造浅沟槽隔离狭缝的方法，其中在半导体本体上形成表面氧化物层和多晶硅缓冲层。 开口形成穿过构成沟槽的各层和身体。 在沟槽和缓冲层表面上形成衬里氧化物层。 在氧化层上沉积厚的氧化层以填充沟槽，并通过化学机械抛光将层平坦化。 去除缓冲层的露出部分，并通过各向异性蚀刻除去水平表面氧化物层部分。

公开(公告)号：US6074905A

公开(公告)日：2000-06-13

申请号：US222285

申请日：1998-12-28

Applicant: Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

Inventor： Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Shan Hou ,  Kuo-Hua Pan

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/66575 ,  H01L21/31111 ,  H01L21/823835 ,  H01L29/665

Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.

Abstract translation: 在光刻期间使用SiON抗反射涂层形成多晶硅线的新方法，其中在蚀刻之后在多晶硅侧壁和有源区表面上形成薄氧化物保护层以防止在集成电路的制造中由于SiON的去除而引起的损坏。 实现了 在硅衬底的表面上设置栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积SiON抗反射涂层。 在SiON抗反射涂层上形成光致抗蚀剂掩模。 SiON抗反射涂层，多晶硅层和栅极氧化物层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖以形成多晶硅线。 多晶硅线路和硅衬底被氧化以在多晶硅线路的侧壁和硅衬底的表面上形成保护氧化物层。 去除SiON抗反射涂层，其中保护性氧化物层保护多晶硅线和硅衬底免于在集成电路器件的制造中完全制造多晶硅线。

公开(公告)号：US20120248515A1

公开(公告)日：2012-10-04

申请号：US13494769

申请日：2012-06-12

Applicant: Ru-Shang HSIAO ,  Nai-Wen CHENG ,  Chung-Te LIN ,  Chien-Hsien TSENG ,  Shou-Gwo WUU

Inventor： Ru-Shang HSIAO ,  Nai-Wen CHENG ,  Chung-Te LIN ,  Chien-Hsien TSENG ,  Shou-Gwo WUU

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.

Abstract translation: 本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。 有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。 有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。 有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色 细胞计数由第一次压力引起。

公开(公告)号：US20110260223A1

公开(公告)日：2011-10-27

申请号：US12768063

申请日：2010-04-27

Applicant: Ru-Shang HSIAO ,  Nai-Wen CHENG ,  Chung-Te LIN ,  Chien-Hsien TSENG ,  Shou-Gwo WUU

Inventor： Ru-Shang HSIAO ,  Nai-Wen CHENG ,  Chung-Te LIN ,  Chien-Hsien TSENG ,  Shou-Gwo WUU

IPC: H01L27/146 ,  H01L21/31 ,  H01L21/66

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

Abstract translation: 上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。 制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。 通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。 如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。 拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

公开(公告)号：US07611937B2

公开(公告)日：2009-11-03

申请号：US11281029

申请日：2005-11-17

Applicant: Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

Inventor： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

Abstract translation: 提供一种形成具有混合晶体取向的半导体结构并形成在半导体结构上具有改进性能的MOSFET的方法。 该方法包括在第一半导体层上提供包括掩埋氧化物（BOX）的衬底和BOX上的第二半导体层，其中第一和第二半导体层分别具有第一和第二晶体取向，并且其中衬底 包括第一区域和第二区域。 在延伸到第一半导体层的第二区域中形成隔离结构。 然后在隔离结构中形成沟槽，暴露第一半导体层。 半导体材料在沟槽中外延生长。 该方法还包括在外延生长的半导体材料上在第二半导体层上形成第一类型的MOSFET和与第一类型相反的MOSFET。

公开(公告)号：US20060292834A1

公开(公告)日：2006-12-28

申请号：US11281029

申请日：2005-11-17

Applicant: Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

Inventor： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US6057207A

公开(公告)日：2000-05-02

申请号：US47542

申请日：1998-03-25

Applicant: Chung-Te Lin ,  Chin-Hsiun Ho

Inventor： Chung-Te Lin ,  Chin-Hsiun Ho

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A method of planarizing a non-conformal oxide layer 40 forming shallow trench isolation between active areas 12 in a substrate. The invention uses a first chemical-mechanical polish (CMP) step to form openings 50 only over wide active areas. An etch is used to remove oxide 40 from only over the wide active areas 12A. A second CMP step is used to planarized the oxide layer 40. The invention begins by forming spaced trenches 30 in said substrate 10 defining active areas 12. A first insulating layer 40 composed of a non-conformal silicon oxide is formed by a HDPCVD process over the substrate and fills the trenches 30. A etch barrier layer 44 is formed over the first insulating layer 40. In a first chemical-mechanical polish (CMP) step, the conformal etch barrier layer 44 over only the wide raised portions 12A is polished to form a self-aligned first openings 50. The chemical-mechanical polishing of the conformal etch barrier layer forms a self-aligned etch mask. The first insulating layer 40 is then etched through at least the first opening 50 to expose a first barrier layer 24 over the wide active areas 12A. In a second CMP step, the etch barrier layer 44 is removed and the first insulating layer 40 is planarized to fill the shallow trenches 30.

Abstract translation: 在衬底中的有源区域12之间形成浅沟槽隔离的非保形氧化物层40的平面化方法。 本发明使用第一化学机械抛光（CMP）步骤仅在宽的有效区域上形成开口50。 使用蚀刻仅从宽的有源区域12A移除氧化物40。 使用第二CMP步骤对氧化物层40进行平坦化。本发明通过在限定有源区域12的所述衬底10中形成间隔开的沟槽30开始。由非保形氧化硅构成的第一绝缘层40通过HDPCVD工艺形成 衬底并填充沟槽30.蚀刻阻挡层44形成在第一绝缘层40的上方。在第一化学机械抛光（CMP）步骤中，只有宽的凸起部分12A上的共形蚀刻阻挡层44被抛光到 形成自对准的第一开口50.保形蚀刻阻挡层的化学机械抛光形成自对准的蚀刻掩模。 然后，通过至少第一开口50蚀刻第一绝缘层40，以在宽的有源区域12A上露出第一阻挡层24。 在第二CMP步骤中，去除蚀刻阻挡层44，并且平坦化第一绝缘层40以填充浅沟槽30。

公开(公告)号：US08778717B2

公开(公告)日：2014-07-15

申请号：US12726215

申请日：2010-03-17

Applicant: Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

Inventor： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC: H01L21/00

CPC classification number: H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

Abstract translation: 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。