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11.发明授权公开(公告)号：US07927895B1
公开(公告)日：2011-04-19
申请号：US12574118
申请日：2009-10-06
IPC分类号： H01L21/00
CPC分类号： H01L22/20 , G01R31/2884 , G01R31/307 , H01L22/12 , H01L22/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for determining resistances of defects in a test structure, comprising: forming a first layer of the test structure having elements under test; generating a first e-beam image of the first layer, the first e-beam image graphically identifying defects detected at the first layer, each defect at the first layer having a corresponding grey scale level; adding capacitance to the structure by forming a metal layer of the structure; generating a second e-beam image of the metal layer, the second e-beam image graphically identifying defects detected at the metal layer, each defect at the metal layer having a corresponding grey scale level; generating a pattern of grey scale levels for each defect based on the corresponding grey scale level of each defect at each layer of the test structure; and determining a resistive range of each defect based on the pattern of grey scale levels generated for each defect.
摘要翻译： 一种确定测试结构中的缺陷电阻的方法，包括：形成具有被测元件的测试结构的第一层; 产生第一层的第一电子束图像，第一电子束图像以图形方式识别在第一层处检测到的缺陷，第一层处的每个缺陷具有相应的灰度级; 通过形成结构的金属层向结构增加电容; 产生所述金属层的第二电子束图像，所述第二电子束图像以图形方式识别在所述金属层处检测到的缺陷，所述金属层处的每个缺陷具有相应的灰度级; 基于测试结构的每个层处的每个缺陷的相应灰度级产生针对每个缺陷的灰度级的图案; 以及基于为每个缺陷生成的灰度级的图案来确定每个缺陷的电阻范围。
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12.发明申请公开(公告)号：US20110080180A1
公开(公告)日：2011-04-07
申请号：US12574118
申请日：2009-10-06
CPC分类号： H01L22/20 , G01R31/2884 , G01R31/307 , H01L22/12 , H01L22/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for determining resistances of defects in a test structure, comprising: forming a first layer of the test structure having elements under test; generating a first e-beam image of the first layer, the first e-beam image graphically identifying defects detected at the first layer, each defect at the first layer having a corresponding grey scale level; adding capacitance to the structure by forming a metal layer of the structure; generating a second e-beam image of the metal layer, the second e-beam image graphically identifying defects detected at the metal layer, each defect at the metal layer having a corresponding grey scale level; generating a pattern of grey scale levels for each defect based on the corresponding grey scale level of each defect at each layer of the test structure; and determining a resistive range of each defect based on the pattern of grey scale levels generated for each defect.
摘要翻译： 一种确定测试结构中的缺陷电阻的方法，包括：形成具有被测元件的测试结构的第一层; 产生第一层的第一电子束图像，第一电子束图像以图形方式识别在第一层处检测到的缺陷，第一层处的每个缺陷具有相应的灰度级; 通过形成结构的金属层向结构增加电容; 产生所述金属层的第二电子束图像，所述第二电子束图像以图形方式识别在所述金属层处检测到的缺陷，所述金属层处的每个缺陷具有相应的灰度级; 基于测试结构的每个层处的每个缺陷的相应灰度级产生针对每个缺陷的灰度级的图案; 以及基于为每个缺陷生成的灰度级的图案来确定每个缺陷的电阻范围。
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公开(公告)号：US07811906B1
公开(公告)日：2010-10-12
申请号：US12612331
申请日：2009-11-04
CPC分类号： H01L21/32139 , H01L21/762
摘要： An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.
摘要翻译： 为了形成绝缘体上的基板，描述了其中在碳层仍然附着到基板上时除去碳层下面的金属模板层的就地结合方法。 在就地接合方法的一个实施例中，在初始衬底结构的绝缘表面层上形成至少一个层状金属/碳（M / C）区域。 所述至少一层分层的M / C区域具有与绝缘表面层的暴露区域相邻的边缘。 然后，至少一层分层M / C区域的一些边缘经由固定结构固定到初始结构的基底，同时其它边缘被暴露。 选择性金属蚀刻剂使用暴露的边缘去除碳层下方的金属层以进入。 在金属蚀刻之后，现在无载体的碳层通过吸引而结合到下面的绝缘表面层。
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14.发明申请ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE 有权使用非晶态Ni合金硅氧烷结构消除金属硅氧烷公开(公告)号：US20080217780A1
公开(公告)日：2008-09-11
申请号：US12105034
申请日：2008-04-17
IPC分类号： H01L23/498
CPC分类号： H01L21/28518 , H01L21/2855
摘要： The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films.
摘要翻译： 本发明提供了一种用于生产薄镍（Ni）一硅化物或NiSi膜（具有约30nm以下的厚度）的方法，作为在退火过程中形成非晶Ni合金硅化物层的CMOS器件中的接触，其消除 （即完全旁路）形成富金属硅化物层。 通过消除富金属硅化物层的形成，与由富金属硅化物相形成的NiSi膜相比，形成的所得NiSi膜具有改善的表面粗糙度。 本发明的方法还形成Ni单硅化物膜，而不会在现有技术的NiSi膜中存在的含Si衬底内遇到掺杂剂类型浓度的任何依赖性。
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公开(公告)号：US09058887B2
公开(公告)日：2015-06-16
申请号：US11928258
申请日：2007-10-30
IPC分类号： G06F17/50 , G11C17/18 , H04L12/701 , H04L29/08
CPC分类号： G11C17/18 , G06F17/5045 , H04L29/08072 , H04L45/00
摘要： The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.
摘要翻译： 本发明提供了一种可再编程的电可熔熔丝和相关的设计结构。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。
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公开(公告)号：US08802563B2
公开(公告)日：2014-08-12
申请号：US13603051
申请日：2012-09-04
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , Y02P80/30 , H01L2924/00
摘要： A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.
摘要翻译： 提供了一种方法，其包括提供具有约4.0或更小的介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与电介质材料的上表面共面的上表面， 所述至少一个导电材料的上表面具有向内延伸到所述至少一个导电材料中的中空金属相关缺陷; 并用表面修复材料填充与中空金属相关的缺陷。
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公开(公告)号：US08772161B2
公开(公告)日：2014-07-08
申请号：US13205063
申请日：2011-08-08
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76828 , H01L21/76886 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/84 , H01L27/1203
摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.
摘要翻译： 提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。 该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。 该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。
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18.发明授权公开(公告)号：US08624395B2
公开(公告)日：2014-01-07
申请号：US13400900
申请日：2012-02-21
申请人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
发明人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。 一种结构包括层间电线之间的交叉处的通孔簇结构。 通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。 至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。
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公开(公告)号：US08564025B2
公开(公告)日：2013-10-22
申请号：US13566594
申请日：2012-08-03
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译： 提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属 多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。
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公开(公告)号：US08445892B2
公开(公告)日：2013-05-21
申请号：US13554065
申请日：2012-07-20
申请人： Guy Cohen , Conal E. Murray , Michael J. Rooks
发明人： Guy Cohen , Conal E. Murray , Michael J. Rooks
IPC分类号： H01L29/775
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/42392 , H01L29/7848 , H01L29/785
摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
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