公开(公告)号：US11681940B2

公开(公告)日：2023-06-20

申请号：US17379172

申请日：2021-07-19

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew Douglas King ,  Alexandre Fréchette ,  Evgeny A. Andriyash ,  Trevor Michael Lanting ,  Emile M. Hoskinson ,  Mohammad H. Amin

IPC: G06N10/00 ,  G06F15/163

CPC classification number: G06N10/00 ,  G06F15/163

Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

公开(公告)号：US20230027682A1

公开(公告)日：2023-01-26

申请号：US17786192

申请日：2020-12-15

Applicant: D-WAVE SYSTEMS INC.

Inventor： Reza Molavi ,  Mark H. Volkmann ,  Emile M. Hoskinson ,  Richard G. Harris ,  Trevor M. Lanting ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06N10/40 ,  H01L39/22

Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.

公开(公告)号：US11526463B2

公开(公告)日：2022-12-13

申请号：US17355458

申请日：2021-06-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/80 ,  H03K3/38 ,  H04L67/12 ,  G06N10/00 ,  G06F15/76 ,  B82Y10/00

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US20220391081A1

公开(公告)日：2022-12-08

申请号：US17855095

申请日：2022-06-30

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Fiona L. Hanington ,  Alexander Condello ,  William W. Bernoudy ,  Melody C. Wong ,  Aidan P. Roy ,  Kelly T. R. Boothby ,  Edward D. Dahl

IPC: G06F3/04847 ,  G06N10/00 ,  G06T11/20 ,  G06F3/04817 ,  G06F16/901

Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.

公开(公告)号：US20220207404A1

公开(公告)日：2022-06-30

申请号：US17607278

申请日：2020-06-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Kelly T.R. Boothby

IPC: G06N10/40 ,  H01L39/22 ,  H01L39/02

Abstract: A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.

公开(公告)号：US11295225B2

公开(公告)日：2022-04-05

申请号：US16029026

申请日：2018-07-06

Applicant: D-Wave Systems Inc.

Inventor： Emile M. Hoskinson ,  Trevor Michael Lanting

IPC: G06N10/00 ,  G06F15/78

Abstract: Passive and actives approaches to mitigating the effects of spin-bath polarization are described and illustrated. Such may, for example, include at least partially depolarizing the spin-bath polarization, for instance by: performing an annealing cycle by the quantum processor to generate a final state of a qubit of the quantum processor; flipping the final state of the qubit of the quantum processor to an opposite state; and latching the qubit in the opposite state for a predetermined duration.

公开(公告)号：US11288073B2

公开(公告)日：2022-03-29

申请号：US16854396

申请日：2020-04-21

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Ilya V. Perminov ,  Mark W. Johnson ,  Christopher B. Rich ,  Fabio Altomare ,  Trevor M. Lanting

IPC: G06F15/76 ,  G06F9/38 ,  G06N10/00 ,  G06F16/901 ,  H01L39/22

Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.

公开(公告)号：US20220076131A1

公开(公告)日：2022-03-10

申请号：US17481568

申请日：2021-09-22

Applicant: D-WAVE SYSTEMS INC.

Inventor： Jason Rolfe

IPC: G06N3/08 ,  G06N10/00 ,  G06N3/04

Abstract: A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior.

公开(公告)号：US20210263643A1

公开(公告)日：2021-08-26

申请号：US17182975

申请日：2021-02-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Fiona L. Hanington ,  Alexander Condello ,  William W. Bernoudy ,  Melody C. Wong ,  Aidan P. Roy ,  Kelly T. R. Boothby ,  Edward D. Dahl

IPC: G06F3/0484 ,  G06N10/00 ,  G06F16/901 ,  G06T11/20 ,  G06F3/0481

Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.

公开(公告)号：US20210190885A1

公开(公告)日：2021-06-24

申请号：US17054631

申请日：2019-05-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  Emile M. Hoskinson ,  Mark H. Volkmann ,  Andrew J. Berkley ,  George E.G. Sterling ,  Jed D. Whittaker

IPC: G01R33/035 ,  H01L39/22 ,  G06N10/00

Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.