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    Method and apparatus to operate a memory cell
    11.
    发明授权
    Method and apparatus to operate a memory cell 有权
    操作存储单元的方法和装置

    公开(公告)号：US06667900B2

    公开(公告)日：2003-12-23

    申请号：US10034331

    申请日：2001-12-28

    Applicant: Tyler Lowrey ,  Daniel Xu

    Inventor： Tyler Lowrey ,  Daniel Xu

    IPC: G11C1115

    CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    Abstract: Briefly, in accordance with an embodiment of the invention, a method and an apparatus to read a phase change memory is provided, wherein the method includes zero biasing unselected memory cells during reading of a selected memory cell.

    Abstract translation: 简而言之，根据本发明的实施例，提供一种读取相变存储器的方法和装置，其中该方法包括在读取所选择的存储单元期间对未选择的存储单元进行零偏置。

    Anti-fuse based programmable serial number generator
    13.
    发明授权
    Anti-fuse based programmable serial number generator 有权
    基于反熔丝的可编程序列号发生器

    公开(公告)号：US08350356B2

    公开(公告)日：2013-01-08

    申请号：US12979265

    申请日：2010-12-27

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L27/06

    CPC classification number: H01L27/0629 ,  H01L27/092

    Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

    Abstract translation: 反熔丝装置包括形成在基板中的第一导电类型的基板和第二导电类型的阱区。 阱区和衬底之间的接合点的特征在于高于预定电压的击穿电压。 该装置包括在该区域内的第二导电类型的接触区域。 该装置还包括衬底内的沟道区域和漏极区域。 栅介质层覆盖沟道区和接触区。 第一多晶硅栅极，漏极区域和阱区域与MOS晶体管相关联。 该装置还包括覆盖在接触区域上的栅极电介质层的第二多晶硅栅极。 接触区域被配置为接收第一电源电压，并且第二多晶硅栅极被配置为接收第二电源电压。

    ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR
    14.
    发明申请
    ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR 有权
    基于反熔丝的可编程序列号发生器

    公开(公告)号：US20120061765A1

    公开(公告)日：2012-03-15

    申请号：US12979265

    申请日：2010-12-27

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L27/06 ,  H01L21/8238

    CPC classification number: H01L27/0629 ,  H01L27/092

    Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

    Abstract translation: 反熔丝装置包括形成在基板中的第一导电类型的基板和第二导电类型的阱区。 阱区和衬底之间的接合点的特征在于高于预定电压的击穿电压。 该装置包括在该区域内的第二导电类型的接触区域。 该装置还包括衬底内的沟道区域和漏极区域。 栅介质层覆盖沟道区和接触区。 第一多晶硅栅极，漏极区域和阱区域与MOS晶体管相关联。 该装置还包括覆盖在接触区域上的栅极电介质层的第二多晶硅栅极。 接触区域被配置为接收第一电源电压，并且第二多晶硅栅极被配置为接收第二电源电压。

    ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES
    15.
    发明申请
    ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES 有权
    嵌入式闪存存储器的阵列架构

    公开(公告)号：US20110298032A1

    公开(公告)日：2011-12-08

    申请号：US12959279

    申请日：2010-12-02

    Applicant: DANIEL XU ,  ROGER LEE

    Inventor： DANIEL XU ,  ROGER LEE

    IPC: H01L29/788 ,  H01L21/336 ,  B82Y40/00

    CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66575 ,  H01L29/78

    Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer.

    Abstract translation: 一种用于制造闪存器件的方法包括在衬底中形成阱区，沉积覆盖阱区的栅极电介质层，以及沉积覆盖栅极电介质层的第一多晶硅层。 该方法还包括沉积覆盖在第一多晶硅层上的介电层，并沉积覆盖介电层的第二多晶硅层以形成堆叠层。 该方法同时对堆叠层进行图案以形成第一闪存单元，其包括覆盖在第一多晶硅层的第一部分上的介电层的第一部分上的第二多晶硅层的第一部分并形成选择器件，其包括 覆盖在第一多晶硅层的第二部分上的介电层的第二部分上的第二多晶硅层的第二部分。 该方法还包括使用离子注入形成源极/漏极区域。 通过向第一多晶硅层的第二部分施加电压来激活选择装置。

    Barrier material encapsulation of programmable material
    16.
    发明授权
    Barrier material encapsulation of programmable material 失效

    公开(公告)号：US07064344B2

    公开(公告)日：2006-06-20

    申请号：US10418548

    申请日：2003-04-17

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L29/06

    CPC classification number: H01L21/76897 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  Y10S438/90 ,  H01L2924/00

    Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

    Forming tapered lower electrode phase-change memories
    18.
    发明授权
    Forming tapered lower electrode phase-change memories 有权
    形成锥形下电极相变存储器

    公开(公告)号：US06933516B2

    公开(公告)日：2005-08-23

    申请号：US10839499

    申请日：2004-05-05

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L45/00 ,  H01L47/00

    CPC classification number: H01L45/06 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

    Abstract translation: 相变存储器可以具有涂覆有绝缘体的锥形下电极。 涂覆的锥形电极用作用于自对准沟槽蚀刻的掩模，以电隔离相邻字线。 在一些实施例中，锥形下电极可以形成在多个掺杂区域上，并且各向同性蚀刻可以用于使电极逐渐变细以及部分下面的掺杂区域。

    Trench sidewall profile for device isolation
    20.
    发明授权
    Trench sidewall profile for device isolation 失效
    用于器件隔离的沟槽侧壁型材

    公开(公告)号：US06514805B2

    公开(公告)日：2003-02-04

    申请号：US09896532

    申请日：2001-06-30

    Applicant: Daniel Xu ,  Erman Bengu ,  Ming Jin

    Inventor： Daniel Xu ,  Erman Bengu ,  Ming Jin

    IPC: H01L2100

    CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L27/24

    Abstract: A method comprising forming a first trench in a substrate, and forming a second trench in the substrate, the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench. An apparatus comprising a matrix of cells in a substrate formed by a plurality of first trenches and a plurality of second trenches, the plurality of second trenches intersecting the plurality of first trenches and having a retrograde sidewall profile relative to a direction from a top to a bottom of the respective trench; and an electrically accessible storage device coupled to respective ones of the matrix of cells.

    Abstract translation: 一种方法，包括在衬底中形成第一沟槽，以及在所述衬底中形成第二沟槽，所述第二沟槽与所述第一沟槽相交并且具有相对于从所述沟槽的顶部到所述沟槽的底部的方向的逆向侧壁轮廓。 一种包括由多个第一沟槽和多个第二沟槽形成的衬底中的单元阵列的装置，所述多个第二沟槽与所述多个第一沟槽相交并且具有相对于从顶部到顶部的方向的逆向侧壁轮廓 相应沟槽的底部; 以及耦合到所述单元阵列中的相应单元的电可存储存储设备。

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