公开(公告)号：US20080220611A1

公开(公告)日：2008-09-11

申请号：US12073502

申请日：2008-03-06

Applicant: Kyung-yub Jeon ,  Myeong-cheol Kim ,  Doo-youl Lee ,  Hak-sun Lee

Inventor： Kyung-yub Jeon ,  Myeong-cheol Kim ,  Doo-youl Lee ,  Hak-sun Lee

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

Abstract translation: 根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻 在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为 蚀刻掩模 该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

公开(公告)号：US20080076047A1

公开(公告)日：2008-03-27

申请号：US11589026

申请日：2006-10-27

Applicant: Yong-jin Chun ,  Doo-youl Lee ,  Moon-hyun Yoo ,  Suk-joo Lee

Inventor： Yong-jin Chun ,  Doo-youl Lee ,  Moon-hyun Yoo ,  Suk-joo Lee

IPC: G03C5/00

CPC classification number: G03F1/36

Abstract: A method of forming an image contour for predicting a pattern image formed on a wafer from a layout of a semiconductor device includes: forming a basic layout for a semiconductor device; performing an optical proximity effect correction (OPC) on the basic layout to form an OPC layout; defining nonlinear regions and linear regions of the basic layout; emulating the nonlinear regions of the basic layout using the OPC layout to form an image contour of the nonlinear regions; determining the linear regions of the basic layout as an image contour of the linear regions; and combining the image contour of the nonlinear regions and image contour of the linear regions to form an image contour of the entire semiconductor device.

Abstract translation: 根据半导体器件的布局形成用于预测在晶片上形成的图案图像的图像轮廓的方法包括：形成用于半导体器件的基本布局; 在基本布局上执行光学邻近效应校正（OPC）以形成OPC布局; 定义基本布局的非线性区域和线性区域; 使用OPC布局模拟基本布局的非线性区域，以形成非线性区域的图像轮廓; 将所述基本布局的线性区域确定为所述线性区域的图像轮廓; 并且组合非线性区域的图像轮廓和线性区域的图像轮廓以形成整个半导体器件的图像轮廓。

公开(公告)号：US20120270365A1

公开(公告)日：2012-10-25

申请号：US13540724

申请日：2012-07-03

Applicant: Young Su KIM ,  Doo-Youl LEE

Inventor： Young Su KIM ,  Doo-Youl LEE

IPC: H01L31/18

CPC classification number: H01L31/022441 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.

Abstract translation: 根据示例性实施例的太阳能电池的制造方法包括：在基板上形成第一掺杂膜; 图案化第一掺杂膜以形成第一掺杂膜图案并且暴露基板的一部分; 在所述第一掺杂膜图案上形成扩散防止膜以覆盖所述基板的所述暴露部分; 蚀刻扩散防止膜，以在第一掺杂膜图案的侧表面上形成间隔物; 在所述第一掺杂膜图案上形成第二掺杂膜以覆盖所述间隔物和暴露的基板; 通过将杂质从第一掺杂膜图案扩散到衬底中而在衬底表面上形成第一掺杂区; 以及通过将杂质从所述第二掺杂膜图案扩散到所述衬底中而在所述衬底表面上形成第二掺杂区域。

公开(公告)号：US20120220071A1

公开(公告)日：2012-08-30

申请号：US13299173

申请日：2011-11-17

Applicant: Young-Su Kim ,  Doo-Youl Lee ,  Sung-Chul Lee

Inventor： Young-Su Kim ,  Doo-Youl Lee ,  Sung-Chul Lee

IPC: H01L31/18 ,  B05C17/06

CPC classification number: B41N1/248 ,  H01L31/022441 ,  Y02E10/50

Abstract: A screen mask has a mesh, a frame, and at least one emulsion pattern. The mesh includes a squeeze surface pressed by a squeegee, and a discharge surface discharging a paste. The frame fixes an edge of the mesh. The emulsion pattern is placed on the discharge surface and includes a main pattern, and an auxiliary pattern spaced apart from the main pattern.

Abstract translation: 屏幕掩模具有网状物，框架和至少一种乳剂图案。 网格包括由刮板压紧的挤压表面和排出浆料的排出表面。 该框架固定网格的边缘。 乳剂图案放置在排出表面上并且包括主图案和与主图案间隔开的辅助图案。

公开(公告)号：US08222129B2

公开(公告)日：2012-07-17

申请号：US12893944

申请日：2010-09-29

Applicant: Young Su Kim ,  Doo-Youl Lee

Inventor： Young Su Kim ,  Doo-Youl Lee

IPC: H01L21/00 ,  H01L21/22

CPC classification number: H01L31/022441 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.

Abstract translation: 根据示例性实施例的太阳能电池的制造方法包括：在基板上形成第一掺杂膜; 图案化第一掺杂膜以形成第一掺杂膜图案并且暴露基板的一部分; 在所述第一掺杂膜图案上形成扩散防止膜以覆盖所述基板的所述暴露部分; 蚀刻扩散防止膜，以在第一掺杂膜图案的侧表面上形成间隔物; 在所述第一掺杂膜图案上形成第二掺杂膜以覆盖所述间隔物和暴露的基板; 通过将杂质从第一掺杂膜图案扩散到衬底中而在衬底表面上形成第一掺杂区; 以及通过将杂质从所述第二掺杂膜图案扩散到所述衬底中而在所述衬底表面上形成第二掺杂区域。

公开(公告)号：US20120107997A1

公开(公告)日：2012-05-03

申请号：US13239197

申请日：2011-09-21

Applicant: Young-Jin KIM ,  Dong-Seop Kim ,  Doo-Youl Lee ,  Jun-Hyun Park ,  Sang-Ho Kim ,  Ju-Hyun Jeong ,  Young-Soo Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Myeong-Woo Kim ,  Sang-Joon Lee

Inventor： Young-Jin KIM ,  Dong-Seop Kim ,  Doo-Youl Lee ,  Jun-Hyun Park ,  Sang-Ho Kim ,  Ju-Hyun Jeong ,  Young-Soo Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Myeong-Woo Kim ,  Sang-Joon Lee

IPC: H01L31/18

CPC classification number: H01L31/0682 ,  H01L31/18 ,  Y02E10/547

Abstract: In a method of manufacturing a solar cell, a first dopant layer is formed on a lower surface of a substrate and a diffusion-preventing layer is formed on an upper surface of the substrate. Then, the first dopant layer is patterned to expose portions of the lower surface of the substrate, and a second dopant layer is formed on the exposed portion of the lower surface of the substrate. A third dopant layer is formed on the diffusion-preventing layer, and the substrate is heated to diffuse dopants from the first, second, and third dopant layers into the substrate, thereby forming semiconductor areas in the substrate.

Abstract translation: 在制造太阳能电池的方法中，在基板的下表面上形成第一掺杂剂层，在基板的上表面形成防扩散层。 然后，将第一掺杂剂层图案化以暴露衬底的下表面的部分，并且在衬底的下表面的暴露部分上形成第二掺杂剂层。 在扩散防止层上形成第三掺杂剂层，并且加热衬底以将掺杂剂从第一，第二和第三掺杂剂层扩散到衬底中，从而在衬底中形成半导体区域。

公开(公告)号：US08026044B2

公开(公告)日：2011-09-27

申请号：US11781987

申请日：2007-07-24

Applicant: Doo-youl Lee ,  Han-ku Cho ,  Suk-joo Lee ,  Gi-sung Yeo ,  Pan-suk Kwak ,  Min-jong Hong

Inventor： Doo-youl Lee ,  Han-ku Cho ,  Suk-joo Lee ,  Gi-sung Yeo ,  Pan-suk Kwak ,  Min-jong Hong

IPC: G03F7/00 ,  G03F7/004 ,  G03F7/20 ,  G03F7/26 ,  G03F7/40

CPC classification number: H01L21/0337

Abstract: A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

Abstract translation: 在半导体衬底上形成精细图案的方法包括形成包括具有特征尺寸F和任意间距P的第一线图案的第一图案，以及形成包括布置在相邻第一线图案之间的第二线图案的第二图案，以形成 具有半间距P / 2的精细图案，第一和第二线图案沿第一方向重复。 在与第一方向垂直的第二方向上的至少一个第一线图案中形成间隙，以通过间隙连接位于第一线图案的每一侧上的第二线图案。 至少一个沿着第一方向延伸的点动图案由与连接的第二线图案相邻的至少一个第一线图案形成。 所述点动图案在所述第二方向上在所连接的第二线图案中的至少一个中形成间隙。

公开(公告)号：US07718504B2

公开(公告)日：2010-05-18

申请号：US11535934

申请日：2006-09-27

Applicant: Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

Inventor： Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

IPC: H01L21/76 ,  H01L21/46

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Abstract translation: 公开了具有对准键的半导体器件及其制造方法。 半导体器件包括具有单元区域和对准键区域的半导体衬底。 限定电池有源区的隔离层设置在半导体衬底的单元区域中。 电池电荷存储层图案跨越电池有源区域设置。 对准电荷存储层图案设置在半导体衬底的对准键区域中。 在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

公开(公告)号：US20080280381A1

公开(公告)日：2008-11-13

申请号：US12219214

申请日：2008-07-17

Applicant: Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

Inventor： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G03F7/40 ,  H01L21/0273

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract translation: 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙

公开(公告)号：US20080203590A1

公开(公告)日：2008-08-28

申请号：US12111651

申请日：2008-04-29

Applicant: Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

Inventor： Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。