-
公开(公告)号：US20120037877A1
公开(公告)日：2012-02-16
申请号：US12855079
申请日：2010-08-12
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
摘要翻译： 所公开的示例性实施例是用于制造相变存储单元的方法。 该方法包括在绝缘衬底内形成非亚光刻通孔。 绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。 通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。 亚光刻孔填充有导电非相变材料。 此外，相变材料沉积在非亚光刻通孔内。
-
公开(公告)号：US08105859B2
公开(公告)日：2012-01-31
申请号：US12556198
申请日：2009-09-09
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译： 一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面 沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面 每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极 。
-
公开(公告)号：US20110037042A1
公开(公告)日：2011-02-17
申请号：US12541595
申请日：2009-08-14
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.
-
公开(公告)号：US07709325B2
公开(公告)日：2010-05-04
申请号：US12043228
申请日：2008-03-06
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/336 , H01L21/44
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The present invention in one embodiment provides a method of forming an electrode that includes the steps of providing at least one metal stud in a layer of an interlevel dielectric material; forming a pillar of a first dielectric material atop the at least one metal stud; depositing an electrically conductive material atop the layer of the interlevel dielectric material and an exterior surface of the pillar, wherein a portion of the electrically conductive material is in electrical communication with the at least one metal stud; forming a layer of a second dielectric material atop the electrically conductive material and the substrate; and planarizing the layer of the second dielectric material to expose an upper surface of the electrically conductive material.
摘要翻译： 本发明在一个实施例中提供了形成电极的方法，其包括以下步骤：在层间电介质材料层中提供至少一个金属柱; 在所述至少一个金属螺柱的顶部上形成第一介电材料的柱; 在所述层间电介质材料的层的顶部和所述柱的外表面之上沉积导电材料，其中所述导电材料的一部分与所述至少一个金属螺柱电连通; 在导电材料和基底之上形成第二电介质材料层; 以及平坦化所述第二电介质材料的层以暴露所述导电材料的上表面。
-
公开(公告)号：US20100078617A1
公开(公告)日：2010-04-01
申请号：US12243759
申请日：2008-10-01
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
摘要翻译： 存储单元结构和形成这种结构的方法。 该方法部分地包括在底部电极的中心上形成氧化层内的通孔。 该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。 通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。 在氧化期间通孔间隔物的膨胀减小了通孔面积。 或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。 第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。 该方法还包括在第一层中氧化通孔的侧壁的至少一部分。
-
公开(公告)号：US07560721B1
公开(公告)日：2009-07-14
申请号：US12035237
申请日：2008-02-21
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
IPC分类号： H01L47/00
CPC分类号： H01L45/141 , G11C13/0004 , G11C13/0007 , G11C2213/52 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145
摘要： The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.
摘要翻译： 本发明在一个实施例中提供了一种包括相变存储单元的存储器件; 第一电极; 以及位于所述相变存储器单元和所述第一电极之间的丝状电阻材料层，其中在所述丝状电阻器材料层的至少一部分中存在至少一个双稳态导电丝状通道，其提供所述相变存储器 电池和第一电极。
-
公开(公告)号：US20090111228A1
公开(公告)日：2009-04-30
申请号：US11924073
申请日：2007-10-25
IPC分类号： H01L21/33
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译： 本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在 最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。
-
公开(公告)号：US07485487B1
公开(公告)日：2009-02-03
申请号：US11970207
申请日：2008-01-07
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.
摘要翻译： 本发明在一个实施例中提供了一种形成存储器件的方法，该存储器件包括：提供包括至少一个通孔的第一介电层，所述通孔包含金属螺柱; 在所述第一电介质层的顶部提供第二电介质层; 使金属螺柱凹陷以暴露通孔的侧壁; 用各向同性蚀刻步骤蚀刻第一介电层中的通孔的侧壁，以产生在第二介电层的一部分下方延伸的底切区域; 在覆盖所述底切区域的所述第二介电层的至少一部分上形成保形绝缘层以提供锁眼; 用各向异性蚀刻蚀刻保形绝缘层以提供露出金属螺柱的套环; 在所述套环内形成与所述金属螺栓接触的阻挡金属; 并形成与阻挡金属接触的相变材料。
-
公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译： 一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面 沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面 每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极 。
-
公开(公告)号：US08518718B2
公开(公告)日：2013-08-27
申请号：US13613313
申请日：2012-09-13
IPC分类号： H01L21/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675
摘要： A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
摘要翻译： 一种用于形成存储器件的方法包括：形成具有在衬底中具有波状轮廓的内表面的空腔，在所述空腔中沉积铁磁材料，在所述衬底上形成接近所述铁磁材料的一部分的读取元件，以及形成 在基板上的写入元件靠近铁磁材料的第二部分。
-
-
-
-
-
-
-
-
-
搜索结果
79 条记录 (耗时 0.02 秒)
