BACKSIDE ILLUMINATED IMAGE SENSOR WITH SHALLOW BACKSIDE TRENCH FOR PHOTODIODE ISOLATION
    11.
    发明申请
    BACKSIDE ILLUMINATED IMAGE SENSOR WITH SHALLOW BACKSIDE TRENCH FOR PHOTODIODE ISOLATION 有权
    背面照明的图像传感器,带有背光隔离膜,用于光电隔离

    公开(公告)号:US20110059572A1

    公开(公告)日:2011-03-10

    申请号:US12944268

    申请日:2010-11-11

    IPC分类号: H01L31/18 H01L31/0216

    摘要: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括实现像素阵列的多个感光元件的传感器层,邻近传感器层的背面的氧化物层以及与传感器层的前侧表面相邻的至少一个电介质层。 传感器层还包括形成在传感器层的背面中的多个背面沟槽,并被布置成在各对感光元件之间提供隔离。 背面沟槽具有形成在传感器层中的相应的背面场隔离注入区域,并且所得结构提供相邻光敏元件之间的载流子复合和串扰的减小。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    Wafer level processing for backside illuminated sensors
    12.
    发明授权
    Wafer level processing for backside illuminated sensors 有权
    背面照明传感器的晶圆级处理

    公开(公告)号:US07859033B2

    公开(公告)日:2010-12-28

    申请号:US12169791

    申请日:2008-07-09

    IPC分类号: H01L31/62

    摘要: A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括传感器层,其具有多个像素阵列的感光元件,邻近传感器层的背面的氧化物层以及与传感器层的前侧表面相邻的至少一个电介质层。 在氧化物层的背面形成有滤色器阵列,在覆盖滤色器阵列的氧化物层的背面附着有透明盖。 再分布金属导体通过介电层中的相应开口与相应的接合焊盘导体电接触。 再分布钝化层形成在再分布金属导体上,并且接触金属化通过再分布钝化层中的相应开口与相应的再分布金属导体中的相应的一个电接触。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    Methods, structures and sytems for an image sensor device for improving quantum efficiency of red pixels
    13.
    发明授权
    Methods, structures and sytems for an image sensor device for improving quantum efficiency of red pixels 有权
    用于提高红色像素量子效率的图像传感器装置的方法,结构和系统

    公开(公告)号:US07821046B2

    公开(公告)日:2010-10-26

    申请号:US11741259

    申请日:2007-04-27

    IPC分类号: H01L31/062

    摘要: A method and structure for providing a high energy implant in only the red pixel location of a CMOS image sensor. The implant increases the photon collection depth for the red pixels, which in turn increases the quantum efficiency for the red pixels. In one embodiment, a CMOS image sensor is formed on an p-type substrate and the high energy implant is a p-type implant that creates a p-type ground contact under the red pixel, thus reducing dark non-uniformity effects. In another embodiment, a CMOS image sensor is formed on an n-type substrate and a high energy p-type implant creates a p-type region under only the red pixel to increase photon collection depth, which in turn increases the quantum efficiency for the red pixels.

    摘要翻译: 一种仅在CMOS图像传感器的红色像素位置提供高能量注入的方法和结构。 植入物增加了红色像素的光子收集深度,这进而提高了红色像素的量子效率。 在一个实施例中,在p型衬底上形成CMOS图像传感器,并且高能量注入是在红色像素之下产生p型接地触点的p型注入,从而减少黑暗的不均匀效应。 在另一个实施例中,CMOS图像传感器形成在n型衬底上,高能p型注入器仅在红色像素下产生p型区域,以增加光子收集深度,这进而提高了量子效率 红色像素。

    WAFER LEVEL PROCESSING FOR BACKSIDE ILLUMINATED SENSORS
    14.
    发明申请
    WAFER LEVEL PROCESSING FOR BACKSIDE ILLUMINATED SENSORS 有权
    背面照明传感器的水平加工

    公开(公告)号:US20100006963A1

    公开(公告)日:2010-01-14

    申请号:US12169791

    申请日:2008-07-09

    IPC分类号: H01L23/02 H01L21/00

    摘要: A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括传感器层,其具有多个像素阵列的感光元件,邻近传感器层的背面的氧化物层以及与传感器层的前侧表面相邻的至少一个电介质层。 在氧化物层的背面形成有滤色器阵列,在覆盖滤色器阵列的氧化物层的背面附着有透明盖。 再分布金属导体通过介电层中的相应开口与相应的接合焊盘导体电接触。 再分布钝化层形成在再分布金属导体上,并且接触金属化通过再分布钝化层中的相应开口与相应的再分布金属导体中的相应的一个电接触。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。

    MEMS package
    15.
    发明授权
    MEMS package 失效
    MEMS封装

    公开(公告)号:US06841861B2

    公开(公告)日:2005-01-11

    申请号:US10716122

    申请日:2003-11-18

    IPC分类号: B81B7/00 H01L21/50 H01L23/02

    CPC分类号: B81B7/007 H01L21/50

    摘要: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate. Metal pads are then formed through the SOI substrate to the metal connectors within the cavity. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element.

    摘要翻译: 用于MEMS应用的晶片级封装工艺,以及由此制造的MEMS封装,其中将SOI晶片结合到MEMS晶片并且通过SOI晶片制造电馈通。 该方法包括提供其上连接有至少一个金属引线的功能元件的第一衬底,以及在其硅部分中提供具有形成在凹腔中的金属连接器的凹腔的第二SOI衬底。 SOI衬底的非凹入表面结合到第一衬底以形成气密密封腔。 在空腔内,金属引线被连接到相应的金属连接器上。 在接合之前,凹腔的深度大于功能元件的厚度,并且小于金属引线及其各自的金属连接器的组合厚度。 在接合之后,去除来自SOI衬底的硅以露出SOI衬底的掩埋氧化物部分。 然后,通过SOI衬底将金属焊盘形成到腔内的金属连接器。 因此,引线接合垫连接到功能元件,而不会将空腔打开到环境中。 然后,电信号可以通过SOI晶片馈送到金属连接器,金属引线和功能元件。

    Increasing the susceptability of an integrated circuit to ionizing radiation
    16.
    发明授权
    Increasing the susceptability of an integrated circuit to ionizing radiation 失效
    增加集成电路对电离辐射的敏感性

    公开(公告)号:US06794733B1

    公开(公告)日:2004-09-21

    申请号:US09590805

    申请日:2000-06-09

    IPC分类号: H01L2358

    摘要: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

    摘要翻译: 在集成电路中,产生了当代加工技术的优点,但由电离辐射造成不可弥补的破坏。 集成电路采用众所周知的现代处理技术设计和制造,除了将某些称为“保护”器件的器件添加到集成电路中。 保护装置被制造成使得它们而不是集成电路上的其他装置对电离辐射敏感。 此外,保护装置以集成电路用电离辐射轰击的方式与集成电路上的超级设备耦合,保护装置短路并破坏了该设备的功能,因此,功能性 集成电路。

    Radiation hardened silicon-on-insulator (SOI) transistor having a body contact
    17.
    发明授权
    Radiation hardened silicon-on-insulator (SOI) transistor having a body contact 有权
    具有身体接触的辐射硬化绝缘体上硅(SOI)晶体管

    公开(公告)号:US06716728B2

    公开(公告)日:2004-04-06

    申请号:US10091664

    申请日:2002-03-05

    IPC分类号: H01L21425

    摘要: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region. These diffusions are ohmically connected to the body region via a body contact, and these diffusions are also connected to the source region by a self-aligned salicide.

    摘要翻译: 公开了辐射硬化绝缘体上硅晶体管。 电介质层设置在基板上,并且晶体管结构设置在电介质层上。 晶体管结构包括体区,源极区,漏极区和栅极层。 主体区域形成在电介质层的第一表面部分上,源区域形成在与第一表面部分相邻的电介质层的第二表面部分上,漏极区域形成在电介质层的第三表面部分上 与第一表面部分相邻,并且栅极层覆盖在主体区域上,并且可操作地在布置在源极区域和漏极区域之间并与其邻接的体区域的该部分中引入通道。 此外,在源区域的两个边缘上放置多个扩散。 这些扩散通过身体接触欧姆连接到身体区域,并且这些扩散也通过自对准的自对准硅胶与源区连接。

    Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
    18.
    发明授权
    Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby 失效
    晶圆级晶圆封装工艺为MEMS和MEMS封装生产

    公开(公告)号:US06660564B2

    公开(公告)日:2003-12-09

    申请号:US10057368

    申请日:2002-01-25

    IPC分类号: H01L2144

    CPC分类号: B81B7/007 H01L21/50

    摘要: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate. Metal pads are then formed through the SOI substrate to the metal connectors within the cavity. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element.

    摘要翻译: 用于MEMS应用的晶片级封装工艺,以及由此制造的MEMS封装,其中将SOI晶片结合到MEMS晶片并且通过SOI晶片制造电馈通。 该方法包括提供其上连接有至少一个金属引线的功能元件的第一衬底,以及在其硅部分中提供具有形成在凹腔中的金属连接器的凹腔的第二SOI衬底。 SOI衬底的非凹入表面结合到第一衬底以形成气密密封腔。 在空腔内,金属引线被连接到相应的金属连接器上。 在接合之前,凹腔的深度大于功能元件的厚度,并且小于金属引线及其各自的金属连接器的组合厚度。 在接合之后,去除来自SOI衬底的硅以露出SOI衬底的掩埋氧化物部分。 然后,通过SOI衬底将金属焊盘形成到腔内的金属连接器。 因此,引线接合垫连接到功能元件,而不会将空腔打开到环境中。 然后,电信号可以通过SOI晶片馈送到金属连接器,金属引线和功能元件。

    Semiconductor device and circuit having low tolerance to ionizing radiation
    19.
    发明授权
    Semiconductor device and circuit having low tolerance to ionizing radiation 有权
    具有低电离辐射耐受性的半导体器件和电路

    公开(公告)号:US06441440B1

    公开(公告)日:2002-08-27

    申请号:US09590806

    申请日:2000-06-09

    IPC分类号: H01L29772

    摘要: Semiconductor devices and integrated circuits that benefit from the advantages of contemporary processing technologies yet are irreparably damaged by ionizing radiation, and methods for making the same. Transistors that are particularly intolerant to ionizing radiation have a gate insulator that includes a portion of a screen layer that is used in conjunction with N- and P-well implantation. After the implantation step, the screen layer exhibits significantly degraded tolerance to ionizing radiation, so that a gate insulator incorporating a portion of such a screen layer will likewise be radiation intolerant. By selectively removing portions of the screen layer, a method is provided for co-locating radiation-tolerant and radiation-intolerant transistors on a substrate. A radiation intolerant integrated circuit is formed by adding “safeguard devices” to an integrated circuit. The safeguard devices are susceptible to relatively low doses of ionizing radiation while other “utile devices” on the integrated circuit are not. The safeguard devices are coupled to the utile devices in such a manner that when the integrated circuit is bombarded with ionizing radiation, the safeguard devices short and destroy the functionality of the utile devices, and, hence, the functionality of the integrated circuit.

    摘要翻译: 受益于当代加工技术优势的半导体器件和集成电路,由电离辐射造成的不可弥补的损害,以及制造这种技术的方法。 对电离辐射特别不耐受的晶体管具有栅极绝缘体,其包括与N-和P-阱注入结合使用的一部分屏幕层。 在植入步骤之后,屏幕层显示出对电离辐射的耐受性显着降低,使得包含这种屏幕层的一部分的栅极绝缘体同样是辐射不耐受的。 通过选择性地去除屏幕层的部分,提供了一种用于在衬底上共放置辐射耐受性和辐射不耐受性晶体管的方法。 通过向集成电路添加“保护装置”来形成辐射不耐受集成电路。 保护装置容易受到相对较低剂量的电离辐射的影响,而集成电路上的其他“超级设备”不是。 保护装置以这样一种方式耦合到该装置,当集成电路用电离辐射轰击时,保护装置短路并破坏了该装置的功能,从而破坏了集成电路的功能。

    Color filter array alignment mark formation in backside illuminated image sensors
    20.
    发明授权
    Color filter array alignment mark formation in backside illuminated image sensors 有权
    背面照明图像传感器中的滤色器阵列对准标记形成

    公开(公告)号:US08017426B2

    公开(公告)日:2011-09-13

    申请号:US12169709

    申请日:2008-07-09

    IPC分类号: H01L21/00

    摘要: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

    摘要翻译: 背面照明图像传感器包括包含像素阵列的感光元件的传感器层,形成在传感器层的前侧表面上的外延层和形成在传感器层的背面上的滤色器阵列。 外延层包括在与传感器层的前侧表面中的各个滤色器阵列对准标记开口对应的位置处形成的多晶硅滤色器阵列对准标记。 滤色器阵列与外延层的滤色器阵列对准标记对准。 图像传感器可以在数字照相机或其他类型的数字成像装置中实现。