-
11.发明授权Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors 失效使用源极线开关晶体管读取，擦除和编程非易失性闪存EEPROM存储器的方法
公开(公告)号：US5587946A
公开(公告)日：1996-12-24
申请号：US212907
申请日：1994-03-15
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C16/02
CPC分类号： G11C16/04 , G11C16/0416 , G11C16/30
摘要： To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.
摘要翻译： 为了减少由于耗尽的存储器阵列单元即使未被选择而导通的读取和写入错误，非选择的存储器单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 非选择单元的阈值电压（即，用于导通的单元的栅极和源极端子之间的最小电压）由于“体效应”而增加，由此阈值电压取决于源极端子与源极端子之间的电压降 基质。 所选单元格的源极线被偏置为大于所选单元的位线的正值。 公开了使用特定电压电平读取，写入和擦除单元的方法。
-
12.发明授权Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process 失效用于测量集成电路中的电介质层的平面度的集成电路和集成电路的工艺和结构，包括用于执行所述工艺的装置
公开(公告)号：US5543633A
公开(公告)日：1996-08-06
申请号：US92717
申请日：1993-07-15
摘要： A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.
摘要翻译： 一种用于测量集成电路中的平面度的方法包括：将待测量的电介质层平坦化地沉积在导电膜的预定测量路径上并测量所述测量路径的电阻。 这种测量路径的电阻在其沉积的表面是完全平坦的时是最小的，并且随着与完美平面性的表面偏差而增加。 描述了包含导电膜的测量部分和导电膜的参考部分的集成电路。
-
13.发明授权Fabrication process for EPROM cells with oxide-nitride-oxide dielectric 失效具有氧化物 - 氮化物 - 氧化物电介质的EPROM电池的制造方法
公开(公告)号：US4808261A
公开(公告)日：1989-02-28
申请号：US40152
申请日：1987-04-20
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/28273 , H01L27/115
摘要： The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.
摘要翻译： 该方法要求用薄的附加多晶硅层覆盖电介质，该多晶硅附加层具有保护电介质不会从随后的掩模引入的任何缺陷的功能。
-
14.发明授权Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors 失效用于制造包括具有自对准硅层和相关晶体管层的非易失性存储单元的集成结构的工艺
公开(公告)号：US4719184A
公开(公告)日：1988-01-12
申请号：US22482
申请日：1987-03-06
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/26
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11543 , H01L27/105 , Y10S438/942
摘要： After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.
摘要翻译： 在栅极氧化物生长之后，沉积和分离第一多晶硅层，电介质氧化物的生长和其从晶体管区域的去除，以及沉积第二多晶层，单个掩模使得可以首先蚀刻第二硅层和 电介质氧化物，然后在电池和晶体管区域的侧面处的栅极氧化物的第一硅层。
-
-
-
搜索结果
14 条记录 (耗时 0.012 秒)
