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    Semiconductor Device and Manufacturing Method thereof
    11.
    发明申请
    Semiconductor Device and Manufacturing Method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20130082362A1

    公开(公告)日：2013-04-04

    申请号：US13510439

    申请日：2011-11-25

    Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L29/02 ,  H01L21/31

    CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

    Abstract translation: 一种半导体器件及其制造方法，其中NMOS器件由通过PECVD具有高紫外光吸收系数的氮化硅膜覆盖，所述氮化硅膜在被受激光激光表面退火时可以很好地吸收紫外光，因此 为了达到良好的脱氢效果，脱氢后，氮化硅膜具有较高的拉伸应力; 由于氮化硅膜具有高的紫外光吸收系数，因此不需要加热基板，从而避免了由于将基板加热脱氢而导致的对器件的不利影响，并且保持了由PECVD工艺引起的热量预算。

    METHOD FOR PLANARIZING INTERLAYER DIELECTRIC LAYER
    12.
    发明申请
    METHOD FOR PLANARIZING INTERLAYER DIELECTRIC LAYER 有权
    用于平面化介质层电介质层的方法

    公开(公告)号：US20120164838A1

    公开(公告)日：2012-06-28

    申请号：US13147044

    申请日：2011-02-17

    Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

    IPC: H01L21/263

    CPC classification number: H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

    Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

    Abstract translation: 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    13.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20120164808A1

    公开(公告)日：2012-06-28

    申请号：US13129419

    申请日：2011-02-17

    Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

    IPC: H01L21/336

    CPC classification number: H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

    Abstract translation: 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

    Nonvolatile memory transistor having poly-silicon fin, stacked nonvolatile memory device having the transistor, method of fabricating the transistor, and method of fabricating the device
    17.
    发明授权
    Nonvolatile memory transistor having poly-silicon fin, stacked nonvolatile memory device having the transistor, method of fabricating the transistor, and method of fabricating the device 失效
    具有多晶硅鳍片的非易失性存储晶体管，具有该晶体管的堆叠式非易失性存储器件，该晶体管的制造方法以及该器件的制造方法

    公开(公告)号：US07842994B2

    公开(公告)日：2010-11-30

    申请号：US12007037

    申请日：2008-01-04

    Applicant: Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu

    Inventor： Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu

    IPC: H01L29/788

    CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/7854

    Abstract: A nonvolatile memory transistor having a poly-silicon fin, a stacked nonvolatile memory device having the transistor, a method of fabricating the transistor, and a method of fabricating the device are provided. The device may include an active fin protruding upward from a semiconductor substrate. At least one first charge storing pattern on a top surface and sidewalls of the active fin may be formed. At least one first control gate line on a top surface of the at least one first charge storing pattern may be formed. The at least one first control gate line may intersect over the active fin. An interlayer dielectric layer may be formed on the at least one first control gate line. A poly-silicon fin may be formed on the interlayer dielectric layer. At least one second charge storing pattern on a top surface and sidewalls of the poly-silicon fin may be formed. At least one second control gate line on a top surface of the at least one second charge storing pattern may be formed, and the at least one second control gate line may intersect over the poly-silicon fin.

    Abstract translation: 提供了具有多晶硅鳍片的非易失性存储晶体管，具有该晶体管的堆叠非易失性存储器件，该晶体管的制造方法以及该器件的制造方法。 该器件可以包括从半导体衬底向上突出的活性鳍片。 可以形成顶表面上的至少一个第一电荷存储图案和有源鳍片的侧壁。 可以形成至少一个第一电荷存储图案的顶表面上的至少一个第一控制栅极线。 至少一个第一控制栅极线可以在有源鳍上交叉。 层间绝缘层可以形成在至少一个第一控制栅极线上。 多晶硅鳍可以形成在层间介电层上。 可以形成多晶硅鳍片的顶表面和侧壁上的至少一个第二电荷存储图案。 可以形成至少一个第二电荷存储图案的顶表面上的至少一个第二控制栅极线，并且所述至少一个第二控制栅极线可以在多晶硅鳍上相交。

    Logic circuits, inverter devices and methods of operating the same
    19.
    发明申请
    Logic circuits, inverter devices and methods of operating the same 失效
    逻辑电路，逆变器及其操作方法

    公开(公告)号：US20090315590A1

    公开(公告)日：2009-12-24

    申请号：US12318727

    申请日：2009-01-07

    Applicant: Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

    Inventor： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

    IPC: H03K19/20 ,  H03K19/0944

    CPC classification number: H03K19/01714

    Abstract: An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.

    Abstract translation: 逆变器装置至少包括连接在电源节点和地之间的第一晶体管。 第一晶体管包括内部电容耦合以控制升压节点处的升压电压的第一栅极和第一端子。 第一端子是第一晶体管的第一源极和第一漏极之一。

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