公开(公告)号：US06518595B2

公开(公告)日：2003-02-11

申请号：US09879317

申请日：2001-06-12

Applicant: Hyung-Dong Lee

Inventor： Hyung-Dong Lee

IPC: H01L310376

CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618

Abstract: A semiconductor memory device that reduces the level of power consumption during a refresh operation includes a controller for generating a refresh signal in response to an auto-refresh signal and a self-refresh signal. The semiconductor memory device further includes a bank counter for generating a bank selection signal and a bank count signal, which are used in selecting a bank in response to the refresh signal, and a bank selector for generating a first and a second bank enable signal that are used to selectively enable each bank in response to the bank selection signal and the bank count signal. Additionally, the semiconductor memory device includes a refresh counter controller for generating a counter active signal in response to the bank selection signal and the refresh signal and a refresh counter for generating a row address signal that is used to access the memory cell in response to the counter active signal.

公开(公告)号：US09043860B2

公开(公告)日：2015-05-26

申请号：US12698668

申请日：2010-02-02

Applicant: Hyung-dong Lee ,  Jung-tae Lee ,  Hee-seon Park ,  Young-in Song ,  Hae-chang Rim

Inventor： Hyung-dong Lee ,  Jung-tae Lee ,  Hee-seon Park ,  Young-in Song ,  Hae-chang Rim

IPC: H04N7/16 ,  H04H20/10 ,  H04N21/235 ,  G06Q30/02 ,  G11B27/30 ,  H04H60/37 ,  H04H60/58 ,  H04H60/59 ,  H04H60/63 ,  H04N21/81 ,  H04N21/8405 ,  H04N21/845

CPC classification number: H04H20/10 ,  G06Q30/02 ,  G06Q30/0255 ,  G11B27/3027 ,  H04H60/37 ,  H04H60/58 ,  H04H60/59 ,  H04H60/63 ,  H04N7/163 ,  H04N21/235 ,  H04N21/812 ,  H04N21/8405 ,  H04N21/8456

Abstract: A method and apparatus for extracting advertisement keywords in association with situations of scenes of video include: establishing a knowledge database including a classification hierarchy for classifying situations of scenes of video and an advertisement keyword list, segmenting a video script corresponding to a received video in units of scenes, and determining a situation corresponding to each scene with reference to the knowledge database, and extracting an advertisement keyword corresponding to the situation of a scene of the received video with reference to the knowledge database.

Abstract translation: 一种用于提取与视频场景相关的广告关键词的方法和装置，包括：建立知识数据库，包括用于分类视频场景的分类等级和广告关键字列表，以单位分割对应于所接收视频的视频脚本 并且参考知识数据库确定与每个场景相对应的情况，并且参考知识数据库提取与接收到的视频的场景的情况相对应的广告关键字。

公开(公告)号：US08531896B2

公开(公告)日：2013-09-10

申请号：US13219656

申请日：2011-08-27

Applicant: Yong Kee Kwon ,  Hyung Dong Lee ,  Young Suk Moon ,  Hyung Gyun Yang ,  Sung Wook Kim

Inventor： Yong Kee Kwon ,  Hyung Dong Lee ,  Young Suk Moon ,  Hyung Gyun Yang ,  Sung Wook Kim

IPC: G11C7/00 ,  G11C7/22 ,  G11C11/22

CPC classification number: G11C7/22 ,  G06F2213/0038 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/22

Abstract: A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.

Abstract translation: 公开了一种半导体系统，半导体存储装置和使用其的数据的输入/输出方法。 半导体系统包括控制器和存储装置，其中控制器被配置为向存储装置发送时钟信号，数据输出命令，地址信号和第二选通信号。 存储装置被配置为与第二选通信号同步地向控制器提供数据，并且响应于从控制器接收到的时钟信号，数据输出命令，地址信号和第二选通信号。

公开(公告)号：US20130094316A1

公开(公告)日：2013-04-18

申请号：US13340868

申请日：2011-12-30

Applicant: Sang Hoon SHIN ,  Hyung Dong LEE ,  Jeong Woo LEE ,  Young Suk MOON

Inventor： Sang Hoon SHIN ,  Hyung Dong LEE ,  Jeong Woo LEE ,  Young Suk MOON

IPC: G11C11/402

CPC classification number: G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

Abstract: A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

Abstract translation: 存储器系统包括：控制器，被配置为提供隐藏的自动刷新命令; 以及被配置为响应于所述隐藏的自动刷新命令执行刷新操作的存储器。 控制器和存储器彼此通信，使得控制器和存储器的每个刷新地址彼此具有相同的值。

公开(公告)号：US08300496B2

公开(公告)日：2012-10-30

申请号：US12948874

申请日：2010-11-18

Applicant: Tae Sik Yun ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

Inventor： Tae Sik Yun ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

IPC: G11C8/18 ,  G11C8/16 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C29/006 ,  G11C29/023

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract translation: 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

公开(公告)号：US20120155200A1

公开(公告)日：2012-06-21

申请号：US13299497

申请日：2011-11-18

Applicant: Young-Suk Moon ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Sang-Hoon Shin

Inventor： Young-Suk Moon ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Sang-Hoon Shin

IPC: G11C8/18 ,  G11C7/12 ,  G11C8/00

CPC classification number: G11C8/12 ,  G06F2213/0038

Abstract: A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory device.

Abstract translation: 存储器系统包括存储器件，被配置为控制存储器件的控制器件，被配置为将控制器件的行命令传送到存储器件的第一通道以及被配置为从控制器件传送列命令的第二通道 到存储设备。

公开(公告)号：US08077529B2

公开(公告)日：2011-12-13

申请号：US12797022

申请日：2010-06-09

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: G11C7/00

CPC classification number: H03K19/094

Abstract: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.

Abstract translation: 半导体存储装置的数据输出电路包括预驱动器，分别根据输出使能信号的状态产生上升沿和下降沿的有效周期中的驱动上升和下降数据的上拉和下拉信号。 主驱动器从上拉和下拉信号产生到公共节点的最后输出数据。 辅助预驱动器产生辅助驱动信号，当上升数据与下降数据不一致时，其与上升数据，下降数据，上升时钟，下降时钟和管道输出控制的输入相对应地被激活 信号。 辅助主驱动器根据辅助驱动信号的状态从上拉和下拉信号产生辅助上一个输出数据到公共节点。

公开(公告)号：US20110024743A1

公开(公告)日：2011-02-03

申请号：US12648680

申请日：2009-12-29

Applicant: Jeong Woo LEE ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

Inventor： Jeong Woo LEE ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  G01R31/2884 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Abstract translation: 半导体集成电路包括具有多个半导体芯片的多芯片封装。 半导体集成电路包括信号线; 以及多个半导体芯片中的半导体芯片中的信号负载补偿部，被配置为响应于测试信号的激活而将设计的信号加载到信号线。 这里，设计的信号负载具有与信号线的多个半导体芯片中的另一半导体芯片的信号负载分量相对应的值。

公开(公告)号：US20100264945A1

公开(公告)日：2010-10-21

申请号：US12829994

申请日：2010-07-02

Applicant: Hyung-Dong LEE

Inventor： Hyung-Dong LEE

IPC: G01R31/02

CPC classification number: G11C29/02 ,  G11C7/08 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/4402

Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

Abstract translation: 半导体集成电路包括用于感测输入数据的读出放大器和用于在测试模式信号被激活时阻塞读出放大器与存储单元之间的信号路径的读出放大器控制器。

公开(公告)号：US07760561B2

公开(公告)日：2010-07-20

申请号：US11638454

申请日：2006-12-14

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: G11C7/22

CPC classification number: H03K19/094

Abstract: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.

Abstract translation: 半导体存储装置的数据输出电路包括预驱动器，分别根据输出使能信号的状态产生上升沿和下降沿的有效周期中的驱动上升和下降数据的上拉和下拉信号。 主驱动器从上拉和下拉信号产生到公共节点的最后输出数据。 辅助预驱动器产生辅助驱动信号，当上升数据与下降数据不一致时，其与上升数据，下降数据，上升时钟，下降时钟和管道输出控制的输入相对应地被激活 信号。 辅助主驱动器根据辅助驱动信号的状态从上拉和下拉信号产生辅助上一个输出数据到公共节点。