公开(公告)号：US20070054445A1

公开(公告)日：2007-03-08

申请号：US11240473

申请日：2005-10-03

Applicant: Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-lyong Choi

Inventor： Hoon Kim ,  In-jae Song ,  Won-joo Kim ,  Byoung-lyong Choi

IPC: H01L21/338 ,  H01L21/461

CPC classification number: H01L21/8238 ,  H01L21/3212 ,  H01L33/08 ,  H01L33/24 ,  Y10S977/755 ,  Y10S977/758 ,  Y10S977/773

Abstract: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

Abstract translation: 提供了一种使用纳米级P-N结器件或使用纳米颗粒的CMOS而不使用掩模或精细图案的纳米级半导体器件的制造方法。 该方法包括在半导体衬底上均匀分散多个纳米颗粒，形成覆盖半导体衬底上的纳米颗粒的绝缘层，部分去除纳米颗粒和绝缘层的上表面，从绝缘体中选择性地除去纳米颗粒 层，并且通过部分地通过去除纳米颗粒形成的空间将半导体衬底部分地掺杂在半导体衬底中部分地形成掺杂半导体层。

公开(公告)号：US20060113552A1

公开(公告)日：2006-06-01

申请号：US11285192

申请日：2005-11-23

Applicant: In-jae Song ,  Byoung-lyong Choi

Inventor： In-jae Song ,  Byoung-lyong Choi

IPC: G05B15/00 ,  H01L21/00 ,  H01L33/00

CPC classification number: H01L33/0058 ,  H01L27/14601 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/14698 ,  H01L27/156 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or a p-type silicon-based substrate; forming a polysilicon having a predetermined depth at one or more predetermined regions of a surface of the substrate in order to form a microdefect flection pattern having a desired microcavity length; oxidizing the surface of the substrate where the polysilicon is formed for forming a silicon oxidation layer on the substrate and forming a microdefect flection pattern having a desired microcavity length at an interface between the substrate and the silicon oxidation layer, wherein the microdefect flection pattern is formed by a difference between an oxidation rate of the polysilicon and an oxidation rate of a material of the substrate during formation of the silicon oxidation layer; exposing the microdefect flection pattern by etching a region of the silicon oxidation layer where the polysilicon is formed; and forming a doping region by doping the exposed microdefect flection pattern in a type opposite to a type of the substrate.

公开(公告)号：US08349076B2

公开(公告)日：2013-01-08

申请号：US11545518

申请日：2006-10-11

Applicant: In-Jae Song ,  Jai-yong Han

Inventor： In-Jae Song ,  Jai-yong Han

IPC: C30B25/00

CPC classification number: C30B33/06 ,  C30B25/183 ,  C30B25/186 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664

Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs. The fabrication method also allows self-separation of thick GaN without cracking, thus achieving a short process time and a high manufacturing yield.

Abstract translation: 制造独立氮化镓（GaN）衬底的方法包括：在反应器内制备GaN衬底; 将HCl和NH 3气体供应到反应器中以处理GaN衬底的表面并形成多孔GaN层; 在多孔GaN层上形成GaN晶体生长层; 并冷却已经形成GaN晶体生长层的GaN衬底，并从衬底分离出GaN晶体生长层。 根据制造方法，在单个反应器内原位进行包括形成多孔GaN层和厚GaN层的整个工艺。 与常规制造方法相比，该方法显着简化。 该制造方法能够在一个室中进行整个工艺，同时使用HVPE工艺气体进行GaN表面处理和生长，从而显着降低制造成本。 制造方法还允许厚的GaN的自分离而不产生裂纹，从而实现短的工艺时间和高的制造成品率。

公开(公告)号：US07537956B2

公开(公告)日：2009-05-26

申请号：US11285192

申请日：2005-11-23

Applicant: In-jae Song ,  Byoung-lyong Choi

Inventor： In-jae Song ,  Byoung-lyong Choi

IPC: H01L21/00

CPC classification number: H01L33/0058 ,  H01L27/14601 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/14698 ,  H01L27/156 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or a p-type silicon-based substrate; forming a polysilicon having a predetermined depth at one or more predetermined regions of a surface of the substrate in order to form a microdefect flection pattern having a desired microcavity length; oxidizing the surface of the substrate where the polysilicon is formed for forming a silicon oxidation layer on the substrate and forming a microdefect flection pattern having a desired microcavity length at an interface between the substrate and the silicon oxidation layer, wherein the microdefect flection pattern is formed by a difference between an oxidation rate of the polysilicon and an oxidation rate of a material of the substrate during formation of the silicon oxidation layer; exposing the microdefect flection pattern by etching a region of the silicon oxidation layer where the polysilicon is formed; and forming a doping region by doping the exposed microdefect flection pattern in a type opposite to a type of the substrate.

Abstract translation: 提供一种制造硅光电子器件的方法，通过该方法制造的硅光电子器件和具有硅光电子器件的图像输入和/或输出装置。 该方法包括：制备n型或p型硅基衬底; 在所述基板的表面的一个或多个预定区域处形成具有预定深度的多晶硅，以便形成具有期望的微腔长度的微缺陷弯曲图案; 氧化形成多晶硅的衬底的表面，以在衬底上形成硅氧化层，并在衬底和硅氧化层之间的界面处形成具有期望的微腔长度的微缺陷弯曲图案，其中形成微缺陷弯曲图案 通过在形成硅氧化层期间多晶硅的氧化速率与衬底的材料的氧化速率之间的差异; 通过蚀刻形成多晶硅的硅氧化层的区域来暴露微缺陷弯曲图案; 以及通过以与衬底类型相反的类型掺杂暴露的微缺陷弯曲图案来形成掺杂区域。

公开(公告)号：US07491997B2

公开(公告)日：2009-02-17

申请号：US11002812

申请日：2004-12-03

Applicant: In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

Inventor： In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

IPC: H01L29/76

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/66833

Abstract: A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.

Abstract translation: 提供了一种存储器件及其制造方法。 该方法包括在半导体衬底上形成栅极叠层，并通过蚀刻栅叠层来部分地暴露半导体衬底的上端部分以形成栅叠层结构，并将掺杂剂注入半导体衬底的暴露部分以形成源极和漏极 区域，其中蚀刻栅极堆叠结构，使得其宽度从顶部向底部增加。 因此，可以使用简化的制造工艺来制造具有高集成度的存储器件。

公开(公告)号：US20070082465A1

公开(公告)日：2007-04-12

申请号：US11545518

申请日：2006-10-11

Applicant: In-Jae Song ,  Jai-yong Han

Inventor： In-Jae Song ,  Jai-yong Han

IPC: H01L21/20

CPC classification number: C30B33/06 ,  C30B25/183 ,  C30B25/186 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664

Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs. The fabrication method also allows self-separation of thick GaN without cracking, thus achieving a short process time and a high manufacturing yield.

Abstract translation: 制造独立氮化镓（GaN）衬底的方法包括：在反应器内制备GaN衬底; 将HCl和NH 3气体供应到反应器中以处理GaN衬底的表面并形成多孔GaN层; 在多孔GaN层上形成GaN晶体生长层; 并冷却已经形成GaN晶体生长层的GaN衬底，并从衬底分离出GaN晶体生长层。 根据制造方法，在单个反应器内原位进行包括形成多孔GaN层和厚GaN层的整个工艺。 与常规制造方法相比，该方法显着简化。 该制造方法能够在一个室中进行整个工艺，同时使用HVPE工艺气体进行GaN表面处理和生长，从而显着降低制造成本。 制造方法还允许厚的GaN的自分离而不产生裂纹，从而实现短的工艺时间和高的制造成品率。