公开(公告)号：US07838790B2

公开(公告)日：2010-11-23

申请号：US11983635

申请日：2007-11-09

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： B07C5/34

CPC分类号： H01L21/67282 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67271 ,  Y10S414/135

摘要： A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

摘要翻译： 提供了一种用于半导体器件的电测试的多功能处理器系统。 多功能处理器系统包括：（1）半导体器件处理部分，包括包括缓冲器的加载单元，包括单独的标记机的分拣单元和卸载单元; （2）与半导体器件处理部分分离的半导体器件测试部分包括测试室，测试室被分离成两个或更多个测试空间，并且测试室的测试空间包括位于下部的第二室 位置，位于第二室上方的第一室以及用于将第一和第二室彼此连接的管道; 和（3）独立地连接到半导体器件处理部分和半导体器件测试部分并且控制托盘信息，测试结果，标记信息和测试程序信息的主计算机。

公开(公告)号：US07772828B2

公开(公告)日：2010-08-10

申请号：US12072444

申请日：2008-02-26

申请人： Chul-woong Jang ,  Seung-ho Jang ,  Jae-il Lee ,  Young-jin Lee

发明人： Chul-woong Jang ,  Seung-ho Jang ,  Jae-il Lee ,  Young-jin Lee

IPC分类号： G01R15/18

CPC分类号： G01R31/31928 ,  G01R31/318516 ,  G01R31/31922 ,  G11C29/56 ,  G11C29/56012

摘要： Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA.

摘要翻译： 自动测试设备能够以低成本和高效率对半导体器件进行高速测试。 自动测试设备（ATE）包括：ATE主体，被配置为电测试半导体器件; 控制ATE上的驱动器和比较器的现场可编程门阵列（FPGA）; 连接到FPGA的输出端的加速器，使FPGA的工作频率加倍; 以及连接到FPGA的输出端子并将从半导体器件传送的数据的工作频率转换为FPGA的工作频率的减速器。

公开(公告)号：US20100117670A1

公开(公告)日：2010-05-13

申请号：US12614504

申请日：2009-11-09

申请人： Ki-jae SONG ,  Hun-Kyo SEO ,  Jae-Il LEE ,  Jong-Won HAN ,  Jong-Pil PARK

发明人： Ki-jae SONG ,  Hun-Kyo SEO ,  Jae-Il LEE ,  Jong-Won HAN ,  Jong-Pil PARK

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R1/06

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

摘要翻译： 用于测试半导体芯片的连接单元和用于测试具有该连接器的半导体芯片的装置包括多个连接器，其上具有一定形式的电连接端子的半导体芯片具有多个孔，电缆被配置为电连接 电连接端子到外部，以及耦合单元，其被配置成选择性地将电缆电连接到电连接端子上。 因此，可以对具有各种电连接端子的图案的半导体芯片进行电气测试，并且一次接收托盘中的半导体芯片。

公开(公告)号：US07554349B2

公开(公告)日：2009-06-30

申请号：US11727938

申请日：2007-03-29

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： G01R31/02

CPC分类号： G01R31/2865 ,  G01R31/2862

摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

摘要翻译： 用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。 测试室可以包括：测试板; 第一个房间 第二个房间 连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。

公开(公告)号：US07084655B2

公开(公告)日：2006-08-01

申请号：US11025092

申请日：2004-12-28

申请人： Byung-Jun Min ,  Woo-Jin Kim ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Hyun-Geun Iy ,  Jae-Il Lee

发明人： Byung-Jun Min ,  Woo-Jin Kim ,  Jeong-Ho Bang ,  Hyun-Seop Shim ,  Hyun-Geun Iy ,  Jae-Il Lee

IPC分类号： G01R31/02

CPC分类号： G01R31/2877 ,  G01R1/0483 ,  G01R31/286 ,  G01R31/2862 ,  G01R31/2879

摘要： A forced air heat exhaust type of burn-in test apparatus for packages: A first air supply duct provides air to the burn-in chamber and a second air supply duct provides air to supply tubes that direst air into the test sockets that hold the packages. The test sockets have a structure that allows air ventilation of the conductive balls. Accordingly, the apparatus can control the temperature around the packages as well as the temperature in the burn-in chamber, thus preventing conductive ball-melting.

摘要翻译： 用于包装的强制空气热排放型老化测试装置：第一供气管道向老化室提供空气，第二空气供应管道提供空气以将管道直接供应到容纳包装的测试插座中 。 测试插座具有允许导电球通风的结构。 因此，该装置可以控制包装周围的温度以及老化室中的温度，从而防止导电性的球熔融。

公开(公告)号：US20060121757A1

公开(公告)日：2006-06-08

申请号：US11295208

申请日：2005-12-05

申请人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

发明人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

IPC分类号： H01R4/58

CPC分类号： G01R1/0483 ,  G01R1/045 ,  G01R1/0466 ,  G01R31/2863

摘要： In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

摘要翻译： 在一个实施例中，使用绝缘硅氧烷粉末和导电粉末的混合物制造连接器。 连接器包括由绝缘硅氧烷粉末形成的连接器主体，并且通过将导电粉末迁移到对应于半导体封装的焊料球的连接部位而形成的或更优选地规则排列的导电硅树脂构件。 导电硅树脂构件包括形成为接近连接器主体的上表面并从其突出的高密度导电硅树脂部件，以及在高密度导电硅树脂部件下方大致垂直取向地形成的低密度导电硅树脂部件， 低密度导电硅部件，其具有从连接器本体的下表面露出的下表面。

公开(公告)号：US06489790B1

公开(公告)日：2002-12-03

申请号：US09519720

申请日：2000-03-07

申请人： Young-soo An ,  Jae-Il Lee ,  Hyo-geun Chae ,  Jeong-ho Bang

发明人： Young-soo An ,  Jae-Il Lee ,  Hyo-geun Chae ,  Jeong-ho Bang

IPC分类号： G01R3102

CPC分类号： G01R1/073 ,  G01R1/0483

摘要： A socket for testing a BGA package capable of avoiding problems like deformation of external terminals of the BGA package or failing to detect a defective BGA package and a test method using the socket are provided. The socket for testing a BGA package connects solder balls (or solder bumps) as external terminals of the BGA package via a mesh, a pressure conductive rubber (PCR) as a middle connection unit, and a channel connection means of a socket board. A plane board having POGO pins or a printed circuit pattern can be used for the channel connection means.

摘要翻译： 提供一种用于测试BGA封装的插座，其能够避免诸如BGA封装的外部端子的变​​形或不能检测到有缺陷的BGA封装的问题以及使用插座的测试方法。 用于测试BGA封装的插座通过网格，作为中间连接单元的压力导电橡胶（PCR）和插座板的通道连接装置将焊球（或焊料凸块）作为BGA封装的外部端子连接。 具有POGO引脚或印刷电路图案的平板可用于通道连接装置。

公开(公告)号：US08889376B2

公开(公告)日：2014-11-18

申请号：US13508002

申请日：2010-08-06

申请人： Jae-Il Lee ,  Young-Sun Lee ,  Tae-Soo Lee

发明人： Jae-Il Lee ,  Young-Sun Lee ,  Tae-Soo Lee

IPC分类号： C07K14/47 ,  C12N15/62 ,  C12N15/63 ,  C07K16/06 ,  C07K16/32

CPC分类号： C07K16/065 ,  C07K16/32 ,  C07K2319/00 ,  C07K2319/70

摘要： A fusion protein that includes a polypeptide binding specifically to a constant region of an antibody and a stabilization protein linked to a terminus of the polypeptide, a polynucleotide encoding the fusion protein, a cell including the polynucleotide, a method of preparing the fusion protein, and a method of isolating an antibody by using the fusion protein.

摘要翻译： 一种融合蛋白，其包括特异性结合抗体的恒定区和连接于多肽的末端的稳定蛋白，编码融合蛋白的多核苷酸，包含多核苷酸的细胞，制备融合蛋白的方法，和 通过使用融合蛋白分离抗体的方法。

公开(公告)号：US07438563B2

公开(公告)日：2008-10-21

申请号：US11295208

申请日：2005-12-05

申请人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

发明人： Young-Bae Chung ,  Hyun-Seop Shim ,  Jeong-Ho Bang ,  Jae-Il Lee ,  Hyun-Kyo Seo ,  Young-Soo An ,  Soon-Geol Hwang

IPC分类号： H01R4/58

CPC分类号： G01R1/0483 ,  G01R1/045 ,  G01R1/0466 ,  G01R31/2863

摘要： In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

摘要翻译： 在一个实施例中，使用绝缘硅氧烷粉末和导电粉末的混合物制造连接器。 连接器包括由绝缘硅氧烷粉末形成的连接器主体，并且通过将导电粉末迁移到对应于半导体封装的焊料球的连接部位而形成的或更优选地规则排列的导电硅树脂构件。 导电硅树脂构件包括形成为接近连接器主体的上表面并从其突出的高密度导电硅树脂部件和在高密度导电硅树脂部件下方基本上垂直取向形成的低密度导电硅树脂部件， 低密度导电硅部件，其具有从连接器本体的下表面露出的下表面。

公开(公告)号：US20070236235A1

公开(公告)日：2007-10-11

申请号：US11727938

申请日：2007-03-29

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： G01R31/02

CPC分类号： G01R31/2865 ,  G01R31/2862

摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

摘要翻译： 用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。 测试室可以包括：测试板; 第一个房间 第二个房间 连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。