公开(公告)号：US07618868B2

公开(公告)日：2009-11-17

申请号：US11381481

申请日：2006-05-03

Applicant: Jae-yoon Yoo ,  Young-gun Ko

Inventor： Jae-yoon Yoo ,  Young-gun Ko

IPC: H01L21/336

CPC classification number: H01L21/823468 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/092

Abstract: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked structure of a second gate insulating layer and a second gate, forming a blocking layer in the first transistor region, conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation in the second transistor region, removing the blocking layer of the first transistor region, forming a pre-spacer layer on the entire surface of the semiconductor substrate, forming a first spacer by anisotropically etching the pre-spacer layer of the first transistor region and forming a second spacer by anisotropically etching the second oxide layer and the pre-spacer layer of the second transistor region, and forming source/drain regions in the semiconductor substrate to complete a first transistor and a second transistor.

Abstract translation: 提供了一种更稳定的半导体集成电路器件及其制造方法。 该方法包括提供一种半导体衬底，其包括具有第一栅极绝缘层和第一栅极的堆叠结构的第一晶体管区域和具有第二栅极绝缘层和第二栅极的堆叠结构的第二晶体管区域，形成阻挡层 在第一晶体管区域中，通过在第二晶体管区域中进行氧化，在第二栅极绝缘层和第二栅极的侧表面上和半导体衬底的暴露表面上保形地形成第二氧化物层，去除第一 晶体管区域，在半导体衬底的整个表面上形成预分隔层，通过各向异性蚀刻第一晶体管区域的预隔离层形成第一间隔物，并通过各向异性蚀刻第二氧化物层和预先形成第二间隔层，形成第二间隔物 - 第二晶体管区域的间隔层，以及在半导体中形成源极/漏极区域 r衬底以完成第一晶体管和第二晶体管。

公开(公告)号：US07385247B2

公开(公告)日：2008-06-10

申请号：US10986018

申请日：2004-11-12

Applicant: Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

Inventor： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC: H01L29/78

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract translation: 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

公开(公告)号：US20080121985A1

公开(公告)日：2008-05-29

申请号：US11557145

申请日：2006-11-07

Applicant: Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

Inventor： Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

IPC: H01L27/088 ,  H01L21/04 ,  H01L29/78 ,  H01L21/77

CPC classification number: H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

Abstract translation: 公开了改进的MOSFET和CMOS结构的实施例，其提供对短沟道效应的增加的控制。 还公开了形成这些结构的相关方法的实施例。 这些实施例通过将掩埋隔离区域并入到源极/漏极延伸区域之下以及深源极/漏极区域和沟道区域之间，特别是在深源极/漏极区域和晕圈区域之间的晶体管中来抑制短沟道效应。 在深源极/漏极区域和沟道区域之间的埋置隔离区域最小化漏极引起的屏障降低（DIBL）以及穿通。 此外，由于深源极/漏极区域和晕圈区域被掩埋隔离区域分开，所以侧壁结电容和结漏电也被最小化。

公开(公告)号：US07368792B2

公开(公告)日：2008-05-06

申请号：US11388868

申请日：2006-03-24

Applicant: Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

Inventor： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC: H01L29/76

CPC classification number: H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract translation: 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US20050023646A1

公开(公告)日：2005-02-03

申请号：US10851336

申请日：2004-05-24

Applicant: Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

Inventor： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

IPC: H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

Abstract: A multi-layered structure of a semiconducotr device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Abstract translation: 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

公开(公告)号：US06486039B2

公开(公告)日：2002-11-26

申请号：US09933039

申请日：2001-08-21

Applicant: Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

Inventor： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

IPC: H01L21302

CPC classification number: H01L21/76229 ,  H01L21/76237

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

公开(公告)号：US07084041B2

公开(公告)日：2006-08-01

申请号：US10795175

申请日：2004-03-05

Applicant: Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

Inventor： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

Abstract: A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

Abstract translation: 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。

公开(公告)号：US20060163558A1

公开(公告)日：2006-07-27

申请号：US11388868

申请日：2006-03-24

Applicant: Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

Inventor： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC: H01L31/109

CPC classification number: H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract translation: 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US06987310B2

公开(公告)日：2006-01-17

申请号：US10851336

申请日：2004-05-24

Applicant: Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

Inventor： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

IPC: H01L31/328 ,  H01L31/72 ,  H01L31/336 ,  H01L31/109 ,  H01L39/60

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

Abstract: A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Abstract translation: 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

公开(公告)号：US06624496B2

公开(公告)日：2003-09-23

申请号：US10044991

申请日：2002-01-15

Applicant: Ja-Hum Ku ,  Dong-Ho Ahn ,  Chul-Sung Kim ,  Jae-Yoon Yoo ,  Sug-Hun Hong ,  Chul-Joon Choi

Inventor： Ja-Hum Ku ,  Dong-Ho Ahn ,  Chul-Sung Kim ,  Jae-Yoon Yoo ,  Sug-Hun Hong ,  Chul-Joon Choi

IPC: H01L2176

CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

Abstract: A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.