公开(公告)号：US20060186505A1

公开(公告)日：2006-08-24

申请号：US10906510

申请日：2005-02-23

Applicant: James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

Inventor： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

IPC: H01L31/06

CPC classification number: H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

Abstract: A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.

Abstract translation: 用于图像传感器单元的结构（及其形成方法）。 该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

公开(公告)号：US20060138480A1

公开(公告)日：2006-06-29

申请号：US10905277

申请日：2004-12-23

Applicant: James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

Inventor： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

IPC: H01L31/113 ,  H01L31/0232 ,  H01L31/00

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20060093924A1

公开(公告)日：2006-05-04

申请号：US10904308

申请日：2004-11-03

Applicant: James Adkisson ,  Eric Coker ,  Christopher Magg ,  Jed Rankin ,  Anthony Stamper

Inventor： James Adkisson ,  Eric Coker ,  Christopher Magg ,  Jed Rankin ,  Anthony Stamper

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/72 ,  G03F1/70

Abstract: A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.

Abstract translation: 用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。 原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。 形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

公开(公告)号：US20060091442A1

公开(公告)日：2006-05-04

申请号：US11298800

申请日：2005-12-09

Applicant: James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

Inventor： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

IPC: H01L29/94

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

Abstract: The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

公开(公告)号：US20060026472A1

公开(公告)日：2006-02-02

申请号：US10710642

申请日：2004-07-27

Applicant: James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

Inventor： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

IPC: G06F17/50 ,  G01R31/28

CPC classification number: G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

Abstract translation: 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

公开(公告)号：US20080108170A1

公开(公告)日：2008-05-08

申请号：US11959841

申请日：2007-12-19

Applicant: James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

Inventor： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

IPC: H01L21/04

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US20070293025A1

公开(公告)日：2007-12-20

申请号：US11849489

申请日：2007-09-04

Applicant: James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

Inventor： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

IPC: H01L21/04

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/045

Abstract: A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.

Abstract translation: 半导体结构制造方法。 首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的 并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向 。 接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。 然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

公开(公告)号：US20070187734A1

公开(公告)日：2007-08-16

申请号：US11276085

申请日：2006-02-14

Applicant: James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

Inventor： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

IPC: H01L31/062

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

Abstract translation: 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

公开(公告)号：US20070026617A1

公开(公告)日：2007-02-01

申请号：US11495518

申请日：2006-07-31

Applicant: James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

Inventor： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

IPC: H01L21/336 ,  H01L27/12 ,  H01L21/20 ,  H01L21/44

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US20060226456A1

公开(公告)日：2006-10-12

申请号：US10907570

申请日：2005-04-06

Applicant: James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Jerome Lasky ,  Richard Phelps

Inventor： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Jerome Lasky ,  Richard Phelps

IPC: H01L31/113

CPC classification number: H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L31/0352

Abstract: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

Abstract translation: 像素传感器单元结构及其制造方法。 像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。 减少了由钉扎层引起的对电荷转移的电势障碍干扰。