Abstract:
Quinazolines of the formula I in which R, R1, R2, R3, R4 and Y have the meaning indicated in Patent Claim 1, and their salts or solvates as glycoprotein IbIX antagonists.
Abstract:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
Abstract:
Quinazolines of the formula (I) in which R, R1, R2, R3, R4 and Y have the meaning indicated in Patent claim 1, and their salts or solvates as glycoprotein IbIX antagonists.
Abstract:
A method of stimulating neuronal growth or repair comprising exposing a target neuron or neuronal area to a solution of the metallothionein isoform MT-IIA.
Abstract:
Quinazolines of the formula (I) in which R, R1, R2, R3, R4 and Y have the meaning indicated in Patent claim 1, and their salts or solvates as glycoprotein 1bIX antagonists.
Abstract:
An integrated housing for a lens and a photodetector, which is being cooled to low temperatures to enable the detector to detect faint emission of photons. An enclosure is provided to which a lens is affixed from one side using a retaining ring, and a photodetector is affixed from the opposite side. The enclosure is affixed to a TE cooler. The enclosure and the retaining ring are made from materials having similar thermal expansion coefficients.
Abstract:
A system for probe-less non-invasive detection of electrical signals from integrated circuit devices is disclosed. The system includes an illumination source, collection optics, imaging optics, and a photon sensor. In a navigation mode, the light source is activated and the imaging optics is used to identify the target area on the chip and appropriately position the collection optics. Once the collection optics is appropriately positioned, the light source is deactivated and the photon sensor is used to detect photons emitted from the chip. No mention of cooling (active device measurement capability) and advanced optics to detect the features (SIL).
Abstract:
The present invention is directed to a latching system that includes a latch assembly, a cup, and a keeper plate. The latch assembly includes a base, a lever, and a catch. The lever is pivotally connected to the base and the catch is pivotally connected to the lever. The base is pivotally attached to the cup such that it rotates about an axis of rotation that is perpendicular in direction in relation to the direction of the axis of rotation of the lever relative to the base. The keeper plate includes a keeper projection. The lever can be lifted and the latch assembly rotated about the axis of rotation of the base to clear the keeper from the catch and thereby allow the opening of a first closure member relative to a second closure member.
Abstract:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
Abstract:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.