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    Mounting structure in integrated circuit module
    11.
    发明授权
    Mounting structure in integrated circuit module 失效
    集成电路模块中的安装结构

    公开(公告)号：US07227258B2

    公开(公告)日：2007-06-05

    申请号：US10988390

    申请日：2004-11-12

    Applicant: Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

    Inventor： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

    IPC: H01L23/34

    CPC classification number: H05K1/181 ,  H01L2924/0002 ,  H05K2201/097 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

    Abstract: Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.

    Abstract translation: 本发明的实施例可以包括用于高密度安装的集成电路模块结构。 一个实施例可以包括布线​​板，具有在其至少一个表面上具有在第一方向上确定的安装长度和在第二方向上确定的安装宽度的安装空间的安装空间以及具有封装安装组合的多个集成电路封装 长度比布线板的安装长度长。 实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。 本实施例可以具有水平和垂直地彼此重叠的封装。 即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

    Clock generator and method of generating a spread spectrum clock (SSC) signal
    12.
    发明申请
    Clock generator and method of generating a spread spectrum clock (SSC) signal 审中-公开
    时钟发生器和产生扩频时钟（SSC）信号的方法

    公开(公告)号：US20060072648A1

    公开(公告)日：2006-04-06

    申请号：US11242913

    申请日：2005-10-05

    Applicant: Jong-hoon Kim ,  Jeong-hyeon Cho

    Inventor： Jong-hoon Kim ,  Jeong-hyeon Cho

    IPC: H04B1/69

    CPC classification number: H03K3/84 ,  G06F1/08 ,  H03K5/13 ,  H03K2005/00019 ,  H04B1/707

    Abstract: A clock generator and method of generating a spread spectrum clock (SSC) signal, in which a delay cell array (DCA) control signal may be output based on one of a received spread spectrum clock generator (SSCG) signal and a feedback signal. The SSC signal may be generated based on at least one of the DCA control signal and a plurality of path control signals. Modulation properties of the SSC signal may be controlled based on a plurality of path control signals.

    Abstract translation: 一种时钟发生器和产生扩展频谱时钟（SSC）信号的方法，其中可以基于接收的扩频时钟发生器（SSCG）信号和反馈信号之一来输出延迟单元阵列（DCA）控制信号。 可以基于DCA控制信号和多个路径控制信号中的至少一个来生成SSC信号。 可以基于多个路径控制信号来控制SSC信号的调制特性。

    Memory module system with efficient control of on-die termination
    13.
    发明申请
    Memory module system with efficient control of on-die termination 有权
    内存模块系统，具有对片上终端的高效控制

    公开(公告)号：US20050212551A1

    公开(公告)日：2005-09-29

    申请号：US10997406

    申请日：2004-11-24

    Applicant: Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

    Inventor： Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

    IPC: G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C11/401 ,  H03K19/003 ,  H04L25/02

    CPC classification number: H04L25/0278 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1084

    Abstract: For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.

    Abstract translation: 对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。 激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。 用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

    Data transmission system and method
    14.
    发明申请
    Data transmission system and method 失效
    数据传输系统及方法

    公开(公告)号：US20050089106A1

    公开(公告)日：2005-04-28

    申请号：US10913359

    申请日：2004-08-09

    Applicant: Jeong-Hyeon Cho ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Byung-Se So

    Inventor： Jeong-Hyeon Cho ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Byung-Se So

    IPC: H04B3/50 ,  H04L25/14 ,  H04B1/69

    CPC classification number: H04L25/14

    Abstract: A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.

    Abstract translation: 一种数据传输系统和方法，其特征在于使用多个差分输出放大器来传输根据从参考数据输出选通信号导出的控制信号而变化的差分数据信号，以及多个差分放大器以接收差分数据信号并检测这些变化 以产生对应于数据输出选通信号的数据输入选通信号。

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