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    Monitoring and control of electronic devices
    11.
    发明申请
    Monitoring and control of electronic devices 审中-公开
    电子设备的监控

    公开(公告)号：US20060276917A1

    公开(公告)日：2006-12-07

    申请号：US11144413

    申请日：2005-06-03

    Applicant: Jinghong Li ,  Robert Lombaerde

    Inventor： Jinghong Li ,  Robert Lombaerde

    IPC: G05B15/00

    CPC classification number: G05B23/0256 ,  G05B23/0216

    Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a Graphical User Interface (GUI) on a computer. The performance of the electronic device is controlled automatically, or by the user through the GUI. The invention also enables automatic testing of the electronic device through the GUI by setting up test configurations, activating test signals, and interpreting any error codes that may be generated. Further, data generated by the monitoring, control and testing of the electronic device can be saved.

    Abstract translation: 一种用于管理一个或多个电子设备的方法，系统和计算机程序产品。 电子设备的性能通过计算机上的图形用户界面（GUI）被监控并呈现给用户。 电子设备的性能可以自动控制，也可以由用户通过GUI进行控制。 本发明还通过设置测试配置，激活测试信号和解释可能产生的任何错误代码，通过GUI自动测试电子设备。 此外，可以节省通过电子设备的监视，控制和测试产生的数据。

    Monolayer dopant embedded stressor for advanced CMOS
    16.
    发明授权
    Monolayer dopant embedded stressor for advanced CMOS 有权
    单层掺杂剂嵌入式应力器用于高级CMOS

    公开(公告)号：US08236660B2

    公开(公告)日：2012-08-07

    申请号：US12764329

    申请日：2010-04-21

    Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    IPC: H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

    Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。

    Monitoring and control of electronic devices
    17.
    发明授权
    Monitoring and control of electronic devices 有权
    电子设备的监控

    公开(公告)号：US08126577B2

    公开(公告)日：2012-02-28

    申请号：US12248594

    申请日：2008-10-09

    Applicant: Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

    Inventor： Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

    IPC: G01B21/00 ,  G05B11/01 ,  G05B13/02 ,  G05B15/00 ,  G05B15/02 ,  G05B23/02 ,  G06F15/00 ,  G09B21/00

    CPC classification number: G05B23/0256

    Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.

    Abstract translation: 一种用于管理一个或多个电子设备的方法，系统和计算机程序产品。 监视电子设备的性能并通过数字代理接口向用户呈现。 电子设备的性能由数字代理通过数字代理接口自动控制。 本发明还能够通过设置测试配置，激活测试信号和解释可能产生的任何错误代码，通过数字代理接口来自动测试电子设备。

    MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS
    19.
    发明申请
    MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 有权
    用于高级CMOS的单层掺杂嵌入式压电器

    公开(公告)号：US20110260213A1

    公开(公告)日：2011-10-27

    申请号：US12764329

    申请日：2010-04-21

    Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

    IPC: H01L29/772 ,  H01L21/335

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

    Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。

    EMBEDDED STRESS ELEMENTS ON SURFACE THIN DIRECT SILICON BOND SUBSTRATES
    20.
    发明申请
    EMBEDDED STRESS ELEMENTS ON SURFACE THIN DIRECT SILICON BOND SUBSTRATES 审中-公开
    表面薄膜直接硅胶基板上的嵌入应力元件

    公开(公告)号：US20100200896A1

    公开(公告)日：2010-08-12

    申请号：US12367561

    申请日：2009-02-09

    Applicant: Thomas N. Adam ,  Jinghong Li ,  Thomas A. Wallner ,  Haizhou Yin

    Inventor： Thomas N. Adam ,  Jinghong Li ,  Thomas A. Wallner ,  Haizhou Yin

    IPC: H01L29/04 ,  H01L21/20 ,  H01L29/161

    CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02573 ,  H01L21/78 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method for growing an epitaxial layer on a substrate wherein the substrate includes a surface having a Miller index of (110) for the beneficial properties. The method comprises using a direct silicon bonded wafer with a substrate having a first Miller index and a surface having a second Miller index. An element such as a gate for a PFET may be deposited onto the surface. The area not under the gate may then be etched away to expose the substrate. An epitaxial layer may then be grown on the surface providing optimal growth patterns. The Miller index of the substrate may be (100). In an alternative embodiment the surface may have a Miller index of (100) and the surface is etched where an element such as a gate for a PFET may be placed.

    Abstract translation: 一种用于在衬底上生长外延层的方法，其中所述衬底包括具有用于有益特性的（110）的米勒指数的表面。 该方法包括使用具有第一米勒指数的基底和具有第二米勒指数的表面的直接硅键合晶片。 诸如用于PFET的栅极的元件可以沉积在表面上。 然后可以蚀刻掉不在栅极下方的区域以露出衬底。 然后可以在表面上生长外延层，提供最佳生长模式。 基板的米勒指数可以是（100）。 在替代实施例中，表面可以具有（100）的米勒指数，并且表面被蚀刻，其中可以放置诸如用于PFET的栅极的元件。

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