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11.发明授权公开(公告)号：US08489839B1
公开(公告)日：2013-07-16
申请号：US12639728
申请日：2009-12-16
IPC分类号： G06F13/16
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/06
摘要： The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.
摘要翻译： 存储器分配器芯片将多个DRAM单元耦合到PPU，从而扩展用于存储数据的PPU的可用存储器容量并增加图形处理系统的整体性能。 当PPU接口和DRAM接口的传输频率和突发长度不同时，存储器分离器芯片包括用于在PPU和DRAM单元之间管理数据传输的逻辑。 具体地，当传输频率或突发长度不同时，存储器分离器芯片实现重叠传输模式，配对传输模式或两种模式的组合。
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公开(公告)号：US08487681B2
公开(公告)日：2013-07-16
申请号：US13033426
申请日：2011-02-23
IPC分类号： H03K3/356
CPC分类号： H03K3/36 , H03K3/012 , H03K3/356121
摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
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公开(公告)号：US20120017048A1
公开(公告)日：2012-01-19
申请号：US13245769
申请日：2011-09-26
申请人： Jonah M. Alben
发明人： Jonah M. Alben
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06T1/60
摘要： Methods, apparatuses, and systems are presented for caching. A cache memory area may be used for storing data from memory locations in an original memory area. The cache memory area may be used in conjunction with a repeatedly updated record of storage associated with the cache memory area. The repeatedly updated record of storage can thus provide a history of data storage associated with the cache memory area. The cache memory area may be loaded with entries previously stored in the cache memory area, by utilizing the repeatedly updated record of storage. In this manner, the record may be used to “warm up” the cache memory area, loading it with data entries that were previously cached and may be likely to be accessed again if repetition of memory accesses exists in the span of history captured by the repeatedly updated record of storage.
摘要翻译： 呈现缓存的方法，设备和系统。 高速缓冲存储器区域可以用于从原始存储器区域中的存储器位置存储数据。 缓存存储器区域可以与与高速缓冲存储器区域相关联的存储器的重复更新的记录结合使用。 因此，重复更新的存储记录可以提供与高速缓冲存储器区域相关联的数据存储的历史。 通过利用重复更新的存储记录，高速缓存存储器区域可以加载先前存储在高速缓冲存储器区域中的条目。 以这种方式，该记录可以用于“预热”高速缓冲存储器区域，用先前缓存的数据条目加载该缓冲存储器区域，并且如果重复存储器访问存在于由 反复更新的存储记录。
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公开(公告)号：US07903123B1
公开(公告)日：2011-03-08
申请号：US11957367
申请日：2007-12-14
申请人： Jonah M. Alben , Stephen Lew
发明人： Jonah M. Alben , Stephen Lew
CPC分类号： G09G3/2048 , G09G5/02 , G09G5/363 , G09G2320/0247
摘要： A programmable system for dithering video data. The system is operable in at least two user-selectable modes which can include a small kernel mode and a large kernel mode. In some embodiments, the system is operable in at least one mode in which it applies two or more kernels (each from a different kernel sequence) to each block of video words. Each kernel sequence repeats after a programmable number of the blocks (e.g., a programmable number of frames containing the blocks) have been dithered. The period of repetition is preferably programmable independently for each kernel sequence. The system preferably includes a frame counter for each kernel sequence. Each counter generates an interrupt when the number of frames of data dithered by kernels of the sequence has reached a predetermined value. In response to the interrupt, software can change the kernel sequence being applied. Typically, the system performs both truncation and dithering on words of video data. For example, some embodiments produce dithered 6-bit color components in response to 8-bit input color component words. Preferably, the inventive system is optionally operable in either a normal mode (in which dithering is applied to all pixels in accordance with the invention) or in an anti-flicker mode. Another aspect of the invention is a computer system in which the dithering system is implemented as a subsystem of a pipelined graphics processor or display device. Another aspect of the invention is a display device that includes an embodiment of the dithering system.
摘要翻译： 用于抖动视频数据的可编程系统。 该系统可操作于至少两个用户可选择的模式，其可以包括小的内核模式和大的内核模式。 在一些实施例中，系统以至少一种模式操作，其中它将两个或更多个内核（每个来自不同的内核序列）应用于每个视频字块。 每个内核序列在可编程数量的块（例如，包含块的可编程帧数）已经被抖动之后重复。 重复的周期优选地针对每个内核序列独立地可编程。 该系统优选地包括用于每个核心序列的帧计数器。 当由序列的内核抖动的数据帧数达到预定值时，每个计数器产生一个中断。 响应中断，软件可以更改正在应用的内核序列。 通常，系统对视频数据的字执行截断和抖动。 例如，一些实施例响应于8位输入颜色分量字而产生抖动的6位颜色分量。 优选地，本发明的系统可选地以正常模式（其中抖动施加到根据本发明的所有像素）或以防闪烁模式操作。 本发明的另一方面是一种计算机系统，其中抖动系统被实现为流水线图形处理器或显示设备的子系统。 本发明的另一方面是包括抖动系统的实施例的显示装置。
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公开(公告)号：US07886164B1
公开(公告)日：2011-02-08
申请号：US10449942
申请日：2003-05-30
申请人： Jonah M. Alben , Kevin Kranzusch
发明人： Jonah M. Alben , Kevin Kranzusch
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/24 , Y02D10/126 , Y02D10/172
摘要： The present invention facilitates processor speed adjustments within acceptable temperature ranges. In one embodiment, a present invention system includes a temperature sensor that senses the temperature of the processor. When the temperature sensor senses the processor temperature approaching predetermined levels one or more adjustments are performed. For example, the adjustment can include automatically increasing or decreasing a voltage level in response to crossing a temperature threshold.
摘要翻译： 本发明便于在可接受的温度范围内的处理器速度调节。 在一个实施例中，本发明系统包括感测处理器的温度的温度传感器。 当温度传感器感测处理器温度接近预定水平时，执行一个或多个调整。 例如，调整可以包括响应于跨越温度阈值而自动增加或减小电压电平。
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公开(公告)号：US07836318B1
公开(公告)日：2010-11-16
申请号：US11561666
申请日：2006-11-20
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译： 用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。 本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。 切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。 在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。 本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。
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公开(公告)号：US07657775B1
公开(公告)日：2010-02-02
申请号：US11944429
申请日：2007-11-22
申请人： Barry Wagner , Jonah M. Alben , Sonny Yeoh , Jeffrey J. Irwin , Saurabh Gupta
发明人： Barry Wagner , Jonah M. Alben , Sonny Yeoh , Jeffrey J. Irwin , Saurabh Gupta
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/324 , Y02D10/126
摘要： Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.
摘要翻译： 用于改变提供给图形存储器的时钟信号的频率的方法，电路和装置，同时减少监视器上的所得到的视觉毛刺或干扰。 具体实施例提供可以被多路复用或选择以提供存储器时钟信号给图形存储器的多个时钟源。 多路复用器从提供第一时钟源信号作为存储器时钟信号切换，以提供第二时钟源信号作为存储器时钟信号。 第一个时钟源改变其操作频率。 在第一个时钟源稳定或稳定后，多路复用器切换回提供第一个时钟源信号作为存储器时钟信号。
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公开(公告)号：US07477257B2
公开(公告)日：2009-01-13
申请号：US11303187
申请日：2005-12-15
CPC分类号： G06F13/1694 , G06T1/60 , G09G5/003 , G09G5/006 , G09G5/363 , G09G5/39 , G09G2360/128
摘要： A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.
摘要翻译： 存储器集线器允许图形处理器访问诸如动态随机存取存储器（DRAM）的随机存取存储器。 在一个实现中，存储器集线器通过聚合两个或更多个存储器的存储器来允许有效存储器带宽的增加。 在另一实现中，存储器集线器允许图形处理器将存储器访问接口操作卸载到存储器集线器。
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19.发明授权公开(公告)号：US07301542B1
公开(公告)日：2007-11-27
申请号：US10954548
申请日：2004-09-29
CPC分类号： G09G5/395 , G06T5/20 , G09G5/391 , G09G2340/02
摘要： A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.
摘要翻译： 图形处理系统在扫描输出操作期间对过采样数据执行滤波。 从过采样帧缓冲区中读取采样值，并在扫描期间进行滤波; 滤波后的颜色值（每像素一个）被提供给显示设备，而没有将经滤波的数据存储在帧缓冲器中的中间步骤。 在一个实施例中，滤波电路包括被配置为从包含过采样数据的帧缓冲器读取对应于采样点的数据值的存储器接口; 以及滤波器，被配置为接收由所述存储器接口提供的数据值，以从所述数据值计算像素值，并且传输所述像素值以供显示设备显示，其中，所述滤波器在扫描输出操作期间计算所述像素值。
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20.发明授权公开(公告)号：US06870542B2
公开(公告)日：2005-03-22
申请号：US10187111
申请日：2002-06-28
CPC分类号： G09G5/395 , G06T5/20 , G09G5/391 , G09G2340/02
摘要： A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.
摘要翻译： 图形处理系统在扫描输出操作期间对过采样数据执行滤波。 从过采样帧缓冲区中读取采样值，并在扫描期间进行滤波; 滤波后的颜色值（每像素一个）被提供给显示设备，而没有将经滤波的数据存储在帧缓冲器中的中间步骤。 在一个实施例中，滤波电路包括被配置为从包含过采样数据的帧缓冲器读取对应于采样点的数据值的存储器接口; 以及滤波器，被配置为接收由所述存储器接口提供的数据值，以从所述数据值计算像素值，并且传输所述像素值以供显示设备显示，其中，所述滤波器在扫描输出操作期间计算所述像素值。
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