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公开(公告)号：US07886164B1
公开(公告)日：2011-02-08
申请号：US10449942
申请日：2003-05-30
申请人： Jonah M. Alben , Kevin Kranzusch
发明人： Jonah M. Alben , Kevin Kranzusch
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/24 , Y02D10/126 , Y02D10/172
摘要： The present invention facilitates processor speed adjustments within acceptable temperature ranges. In one embodiment, a present invention system includes a temperature sensor that senses the temperature of the processor. When the temperature sensor senses the processor temperature approaching predetermined levels one or more adjustments are performed. For example, the adjustment can include automatically increasing or decreasing a voltage level in response to crossing a temperature threshold.
摘要翻译： 本发明便于在可接受的温度范围内的处理器速度调节。 在一个实施例中，本发明系统包括感测处理器的温度的温度传感器。 当温度传感器感测处理器温度接近预定水平时，执行一个或多个调整。 例如，调整可以包括响应于跨越温度阈值而自动增加或减小电压电平。
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公开(公告)号：US07849332B1
公开(公告)日：2010-12-07
申请号：US10448891
申请日：2003-05-30
申请人： Jonah M. Alben , Kevin Kranzusch
发明人： Jonah M. Alben , Kevin Kranzusch
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention facilitates maintenance of processor speed by voltage level adjustment. In one embodiment, a present invention voltage adjustment system includes a speed analysis component that compares an actual speed of a processing unit to a directed speed. If the actual speed is lower than the directed speed, a voltage control component directs offset adjustments in a voltage level of a power signal to the processor. For example, the voltage control component directs an increases in a voltage level of a power signal. The voltage level can be altered to compensate for variations in hardware tolerance variations. In one embodiment of the present invention, a voltage sensor measures the actual voltage of the processing unit.
摘要翻译： 本发明有助于通过电压电平调整来维持处理器速度。 在一个实施例中，本发明的电压调节系统包括将处理单元的实际速度与定向速度进行比较的速度分析组件。 如果实际速度低于定向速度，则电压控制部件将功率信号的电压电平的偏移调整引导到处理器。 例如，电压控制部件引导电力信号的电压电平的增加。 可以改变电压电平以补偿硬件容差变化的变化。 在本发明的一个实施例中，电压传感器测量处理单元的实际电压。
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公开(公告)号：US09164766B1
公开(公告)日：2015-10-20
申请号：US11102189
申请日：2005-04-08
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/4401 , G06F9/5016 , G06F2209/509
摘要： Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.
摘要翻译： 用于以硬件辅助堆栈的形式提供附加存储的方法和装置，其可由运行有限资源的环境的软件使用。 作为示例，硬件辅助堆栈可以向在其有限的分配的地址空间内可访问的VBIOS代码提供额外的堆栈空间。
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公开(公告)号：US20120212271A1
公开(公告)日：2012-08-23
申请号：US13033426
申请日：2011-02-23
IPC分类号： H03K3/02
CPC分类号： H03K3/36 , H03K3/012 , H03K3/356121
摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
摘要翻译： 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。
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5.发明授权Apparatus, system, and method for distributing work to integrated heterogeneous processors 有权用于将工作分配到集成异构处理器的装置，系统和方法公开(公告)号：US08203562B1
公开(公告)日：2012-06-19
申请号：US12243766
申请日：2008-10-01
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
CPC分类号： G06F15/16 , G06F9/5044 , G06T1/20 , G06T15/005 , G09G5/363 , G09G2330/021 , G09G2360/06 , Y02D10/22
摘要： An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.
摘要翻译： 集成电路包括至少两种不同类型的处理器，诸如图形处理器和视频处理器。 通常由两种不同类型的处理器支持至少一种操作。 对于被调度的每个通常支持的操作，作出决定以确定将选择哪种类型的处理器来实现该操作。
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公开(公告)号：US07586492B2
公开(公告)日：2009-09-08
申请号：US11019414
申请日：2004-12-20
申请人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
发明人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
CPC分类号： G09G5/363 , G06F3/1431 , G06T15/005 , G09G5/001 , G09G5/393 , G09G5/395 , G09G5/399 , G09G2310/04 , G09G2360/125 , G09G2360/127
摘要： In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.
摘要翻译： 在图形处理器中，渲染对象和后处理对象与可编程执行核共享对主处理器的访问。 渲染对象从几何数据生成图像的碎片数据。 后处理对象操作以从片段数据生成像素数据帧，并将像素数据存储在帧缓冲器中。 与主处理器的操作并行，扫描引擎引擎读取先前产生的帧的像素数据，并将像素数据提供给显示设备。 扫描引擎周期性地触发主处理器来操作后处理对象以产生下一帧。 可以控制扫描输出引擎和后处理对象之间的时序，使得当扫描引擎引擎完成读取当前帧时，待显示的下一帧准备在帧缓冲器中。
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公开(公告)号：US07355602B1
公开(公告)日：2008-04-08
申请号：US10985699
申请日：2004-11-10
申请人： Mark J. Kilgard , Jonah M. Alben , Cass W. Everitt
发明人： Mark J. Kilgard , Jonah M. Alben , Cass W. Everitt
IPC分类号： G09G5/36
CPC分类号： G06T11/40
摘要： Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.
摘要翻译： 使用代理模板缓冲液清除高效清除模板缓冲器的方法和装置。 硬件寄存器跟踪自上次实际清除以来模板缓冲区的代理清除次数。 每个模板寄存器保留位，用于存储上一次模板寄存器保持分配值时清除其他模板寄存器的代理清除号。 硬件寄存器的内容和每个模板寄存器中的保留位之间的比较确定每个模板寄存器是否应被分配一个清零的值。 如果数字不匹配，模板寄存器将分配一个预定的代理清除值。 在某些应用中，保留位的数量是固定的，而在其他应用中，可以由设计者或软件来设置保留位数。
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公开(公告)号：US07042263B1
公开(公告)日：2006-05-09
申请号：US10742572
申请日：2003-12-18
IPC分类号： H03K3/356
CPC分类号： G06F1/325 , G06F1/08 , G06F1/12 , G06F1/3215
摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
摘要翻译： 通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。 为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。 同步器电路也可用作通用应用时钟发生器。
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公开(公告)号：US06982722B1
公开(公告)日：2006-01-03
申请号：US10233657
申请日：2002-09-03
申请人： Jonah M. Alben , Stephen Lew
发明人： Jonah M. Alben , Stephen Lew
IPC分类号： G09G5/02
CPC分类号： G09G3/2048 , G09G5/02 , G09G5/363 , G09G2320/0247
摘要： A programmable system for dithering video data. The system is operable in at least two user-selectable modes which can include a small kernel mode and a large kernel mode. In some embodiments, the system is operable in at least one mode in which it applies two or more kernels (each from a different kernel sequence) to each block of video words. Each kernel sequence repeats after a programmable number of the blocks (e.g., a programmable number of frames containing the blocks) have been dithered. The period of repetition is preferably programmable independently for each kernel sequence. The system preferably includes a frame counter for each kernel sequence. Each counter generates an interrupt when the number of frames of data dithered by kernels of the sequence has reached a predetermined value. In response to the interrupt, software can change the kernel sequence being applied. Typically, the system performs both truncation and dithering on words of video data. For example, some embodiments produce dithered 6-bit color components in response to 8-bit input color component words. Preferably, the inventive system is optionally operable in either a normal mode (in which dithering is applied to all pixels in accordance with the invention) or in an anti-flicker mode. Another aspect of the invention is a computer system in which the dithering system is implemented as a subsystem of a pipelined graphics processor or display device. Another aspect of the invention is a display device that includes an embodiment of the dithering system.
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公开(公告)号：US06812927B1
公开(公告)日：2004-11-02
申请号：US10175199
申请日：2002-06-18
申请人： Scott P. Cutler , Jonah M. Alben
发明人： Scott P. Cutler , Jonah M. Alben
IPC分类号： G06T120
CPC分类号： G06T1/20
摘要： A system and method are provided for reducing the number of depth clear operations in a hardware graphics pipeline. Initially, a frame count is stored into a frame buffer associated with the hardware graphics pipeline. The stored frame count is associated with a pixel. A depth clear operation is then performed based at least in part on the frame count utilizing the hardware graphics pipeline.
摘要翻译： 提供了一种用于减少硬件图形管线中的深度清除操作的数量的系统和方法。 最初，将帧计数存储到与硬件图形流水线相关联的帧缓冲器中。 存储的帧计数与像素相关联。 然后至少部分地基于使用硬件图形管线的帧计数来执行深度清晰操作。
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