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    Interleaving apparatuses and memory controllers having the same
    13.
    发明授权
    Interleaving apparatuses and memory controllers having the same 有权
    具有相同的交错装置和存储器控制器

    公开(公告)号：US08812942B2

    公开(公告)日：2014-08-19

    申请号：US12944807

    申请日：2010-11-12

    Applicant: Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

    Inventor： Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

    IPC: G06F11/00

    CPC classification number: G06F12/0607 ,  G06F2212/7208

    Abstract: An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

    Abstract translation: 交错装置可以包括：第一缓冲器单元，被配置为以具有扇区大小的单位缓冲输入数据以产生扇区单元数据;编码单元，被配置为对扇区单元数据进行编码，并且基于编码生成多个奇偶校验码， 第二缓冲器单元，被配置为交织扇区单元数据和奇偶校验码，并且基于交织产生交织数据，第二缓冲单元包括被配置为存储交织数据的多个输出缓冲器，以及输出单元，其被配置为输出交织 数据。

    Method and memory system using a priori probability information to read stored data
    16.
    发明授权
    Method and memory system using a priori probability information to read stored data 有权
    使用先验概率信息读取存储数据的方法和存储系统

    公开(公告)号：US08631306B2

    公开(公告)日：2014-01-14

    申请号：US12985397

    申请日：2011-01-06

    Applicant: Ki jun Lee ,  Hong Rak Son ,  Jun jin Kong

    Inventor： Ki jun Lee ,  Hong Rak Son ,  Jun jin Kong

    IPC: H03M13/00 ,  H03M13/03 ,  G11C29/00

    CPC classification number: G11C11/5642 ,  G11C16/349

    Abstract: A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.

    Abstract translation: 存储器系统包括存储用户数据和关于用户数据的状态信息的非易失性存储器件。 在非易失性存储器件的读取操作中，存储器控制器基于状态信息计算用户数据的先验概率，基于先验概率计算后验概率，并执行软判决操作以确定值 基于后验概率的用户数据。

    FLASH MEMORY DEVICE AND RELATED PROGRAMMING METHOD
    18.
    发明申请
    FLASH MEMORY DEVICE AND RELATED PROGRAMMING METHOD 有权
    闪存存储器件及相关编程方法

    公开(公告)号：US20110093765A1

    公开(公告)日：2011-04-21

    申请号：US12769692

    申请日：2010-04-29

    Applicant: Ki jun Lee ,  Hong Rak Son ,  Jun jin Kong

    Inventor： Ki jun Lee ,  Hong Rak Son ,  Jun jin Kong

    IPC: G11C16/06 ,  H03M13/05 ,  G06F11/10 ,  H03M13/19 ,  H03M13/45

    CPC classification number: G11C16/26 ,  G06F11/1072 ,  G11C16/06

    Abstract: A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol.

    Abstract translation: 非易失性存储器件包括被配置为存储每个存储器单元的一个或多个位的存储器单元阵列，被配置为访问存储单元阵列的读取和写入电路，被配置为控制读取和写入电路以顺序执行读取操作的控制逻辑组件 选择的存储单元至少两次以输出读取数据符号;以及纠错单元，被配置为基于所读取的数据符号的图案校正所读取的数据符号中的错误，以输出纠错符号。

    Dual control analog delay element
    20.
    发明授权
    Dual control analog delay element 失效
    双控制模拟延迟元件

    公开(公告)号：US08063687B2

    公开(公告)日：2011-11-22

    申请号：US11833559

    申请日：2007-08-03

    Applicant: Ki-Jun Lee ,  Gurpreet Bhullar

    Inventor： Ki-Jun Lee ,  Gurpreet Bhullar

    IPC: H03H11/26

    CPC classification number: H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

    Abstract: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

    Abstract translation: 用于延迟输入时钟信号以产生输出时钟信号的模拟延迟元件。 模拟延迟元件包括用于接收输入时钟信号并响应于第一偏置电压提供中间时钟信号的延迟电路。 电流镜放大器响应于中间时钟信号在第一电流分支中产生第一电流，并响应于第一电流和第二偏置电压在第二电流分支中产生第二电流。 第二电流分支具有用于提供具有与延迟的中间时钟信号逻辑电平相对应的逻辑电平的输出时钟信号的输出节点。

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