公开(公告)号：US20080144414A1

公开(公告)日：2008-06-19

申请号：US12021762

申请日：2008-01-29

申请人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US20060176758A1

公开(公告)日：2006-08-10

申请号：US11344018

申请日：2006-01-31

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative voltage are adjusted to a negative voltage. The negatively biased word line scheme may decrease influx of discharge current into the negative voltage source and decrease negative voltage fluctuations and associated noise.

摘要翻译： 公开了具有负偏置子字线方案的半导体存储器件及其驱动方法。 在半导体存储器件中，将用于将字线使能信号和字线驱动信号下拉到负电压的NMOS晶体管调节到负电压。 负偏置字线方案可以减少放电电流进入负电压源的流入，并减少负电压波动和相关噪声。

公开(公告)号：US06774712B2

公开(公告)日：2004-08-10

申请号：US10331602

申请日：2002-12-31

申请人： Sang-Jae Rhee ,  Jae-Yoon Sim ,  Sang-Pyo Hong ,  Ki-Chul Chun

发明人： Sang-Jae Rhee ,  Jae-Yoon Sim ,  Sang-Pyo Hong ,  Ki-Chul Chun

IPC分类号： G05F110

CPC分类号： G05F1/465

摘要： In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

摘要翻译： 在该电路中，响应于正常操作模式，提供或降低外部电压源，以向内部电路提供第一电平的内部电压源。 响应于与正常模式具有互补关系的低功耗模式，外部电压源被转换成低于第一电平的第二电平的电压。

公开(公告)号：US07791959B2

公开(公告)日：2010-09-07

申请号：US11708321

申请日：2007-02-21

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C5/14

CPC分类号： H01L23/34 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory integrated circuit device may include a first temperature sensing unit, a first voltage adjusting unit, and a MOS back bias voltage outputting unit. The first voltage adjusting unit may be configured to output a voltage based on an output signal of the temperature sensing unit such that the voltage output changes based on changes in a sensed temperature. The MOS back bias voltage outputting unit may be configured to receive the voltage output by the voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit.

摘要翻译： 存储器集成电路装置可以包括第一温度感测单元，第一电压调节单元和MOS背置偏置电压输出单元。 第一电压调整单元可以被配置为基于温度感测单元的输出信号输出电压，使得电压输出基于感测温度的变化而改变。 MOS背偏置电压输出单元可以被配置为接收由电压调节单元输出的电压，并且被配置为基于第一电压调节单元输出的电压来输出MOS反向偏置电压。

公开(公告)号：US07209399B2

公开(公告)日：2007-04-24

申请号：US11180832

申请日：2005-07-13

申请人： Ki-chul Chun ,  Chang-ho Shin

发明人： Ki-chul Chun ,  Chang-ho Shin

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than or smaller than a voltage VCCA/2 using an auxiliary circuit is used to increase a gate-source voltage of transistors included in each sense amplification circuit. Also, when cell data is 1 and 0, a dummy cell can maintain a voltage difference between the bitlines BL and BLB generated after charge sharing. Furthermore, a sense amplification circuit, which is controlled by an offset control circuit, can remove a threshold voltage offset between the transistors included in each sense amplification circuit. At this time, an auxiliary circuit is used to stabilize the voltage difference.

摘要翻译： 提供了集成电路存储器的位线驱动电路，其增强了预充电方案和感测放大方案和位线驱动方法。 在位线驱动电路中，使用使用辅助电路将位线预充电至大于或小于电压VCCA / 2的电压的新方案用于增加每个读出放大电路中包括的晶体管的栅极 - 源极电压。 此外，当单元数据为1和0时，虚设单元可以维持电荷共享后产生的位线BL和BLB之间的电压差。 此外，由偏移控制电路控制的感测放大电路可以去除每个感测放大电路中包括的晶体管之间的阈值电压偏移。 此时，使用辅助电路来稳定电压差。

公开(公告)号：US20060023537A1

公开(公告)日：2006-02-02

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.

摘要翻译： 公开了一种半导体存储器件及其位线检测方法。 半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为 应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号 其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个 施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

公开(公告)号：US20050057983A1

公开(公告)日：2005-03-17

申请号：US10942829

申请日：2004-09-17

申请人： Ki-Chul Chun

发明人： Ki-Chul Chun

IPC分类号： G11C11/4096 ,  G11C7/00 ,  G11C7/10

CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1051

摘要： A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

摘要翻译： 一种具有数据输出电路的半导体存储器件，其使用熔丝灵活地设定驱动器强度的初始值。

公开(公告)号：US20110114955A1

公开(公告)日：2011-05-19

申请号：US12943345

申请日：2010-11-10

申请人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-soo Jung

发明人： Ki-Chul Chun ,  Hwan Kim ,  Deuk-soo Jung

IPC分类号： H01L33/08 ,  H01L33/16

CPC分类号： H01L27/088 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/40 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An array substrate for a liquid crystal display device includes first and second lines on a substrate and spaced apart from each other, the first and second lines formed of a first metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove, the groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode on the semiconductor layer and connected to the data line; a drain electrode on the semiconductor layer and spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing a portion of the gate insulating layer and an end of the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening, the pixel electrode contacting the end of the drain electrode.

摘要翻译： 液晶显示装置用阵列基板包括基板上的第一线和第二线，彼此间隔开，第一线和第二线由第一金属材料形成; 连接到第一线的栅电极; 所述第一和第二线路上的栅极绝缘层和所述栅极电极并且包括沟槽，所述沟槽暴露所述衬底并且位于所述第一和第二线之间; 栅极绝缘层上的半导体层，并对应于栅电极; 跨越第一和第二线路以及栅极绝缘层的数据线; 半导体层上的源电极并连接到数据线; 半导体层上的漏电极，与源电极间隔开; 数据线上的钝化层，源电极和漏极，并且包括开口，该开口暴露栅极绝缘层的一部分和漏电极的端部; 以及像素电极，位于所述栅极绝缘层上且在所述开口中，所述像素电极与所述漏极的端部接触。

公开(公告)号：US07710807B2

公开(公告)日：2010-05-04

申请号：US12021762

申请日：2008-01-29

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US07576589B2

公开(公告)日：2009-08-18

申请号：US11360106

申请日：2006-02-22

申请人： Ki-Chul Chun ,  Chang-Ho Shin

发明人： Ki-Chul Chun ,  Chang-Ho Shin

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/145 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/075

摘要： A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

摘要翻译： 半导体器件的升压电压产生电路包括具有转移晶体管的主泵电路，主泵电路，用于升压升压节点的电压，并响应于所述转换晶体管，通过转移晶体管将电荷从升压节点传送到输出节点 至少一个控制信号，以及被配置为升高转移晶体管的端子的电压的附加泵浦电路。