公开(公告)号：US20050089594A1

公开(公告)日：2005-04-28

申请号：US10901039

申请日：2004-07-29

Applicant: Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

Inventor： Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

IPC: B29C45/14 ,  B29C45/76

CPC classification number: B29C45/7646 ,  B29C45/14639 ,  B29C2945/76056 ,  B29C2945/76063 ,  B29C2945/7626

Abstract: A molding apparatus mainly comprises a mold chase holder, a mold chase, a heater and a molding flowability sensor. The mold chase comprises a mold cavity and a via, wherein the via penetrates a mold-cavity surface of the mold cavity. The mold chase is accommodated by a mold chase holder and there is a heater, for heating the mold chase up, disposed therein. And the molding flowability sensor for measuring the molding flowability of the instant molding flow at the mold-cavity surface of the mold cavity is provided at the mold-cavity surface of the mold cavity.

Abstract translation: 成型装置主要包括模具支架，模具追踪器，加热器和成型流动性传感器。 模具追逐包括模腔和通孔，其中所述通孔穿过模腔的模腔表面。 模具追逐由模具夹持器容纳，并且设置有用于加热模具追加的加热器。 并且用于测量模腔的模腔表面处的即时成型流的成型流动性的成型流动性传感器设置在模腔的模腔表面。

公开(公告)号：US6093960A

公开(公告)日：2000-07-25

申请号：US330036

申请日：1999-06-11

Applicant: Su Tao ,  Kuang-Lin Lo ,  Hsin-Hsing Wei

Inventor： Su Tao ,  Kuang-Lin Lo ,  Hsin-Hsing Wei

IPC: H01L23/433 ,  H01L23/48 ,  H01L23/28 ,  H01L29/44

CPC classification number: H01L23/4334 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3025

Abstract: A semiconductor package has a die and a plurality of leads electrically connected to the die with bonding wires. A heat spreader has an upper face thermally contacted with the die. The heat spreader is formed by a copper core having at least a portion of surface sequentially coated with a metal medium layer and an insulation layer, wherein the metal medium layer has an adhesion degree with insulation material higher than copper. A package body encapsulates the die, the heat spreader and the plurality of leads, wherein the surface area of the heat spreader that contacts with the package body is coated with the metal medium layer and the insulation layer.

Abstract translation: 半导体封装具有管芯和多个引线，其使用接合线电连接到管芯。 散热器具有与模具热接触的上表面。 散热器由铜芯形成，铜芯具有依次涂覆有金属介质层和绝缘层的表面的至少一部分，其中金属介质层具有高于铜的绝缘材料的粘合度。 包装体封装模具，散热器和多个引线，其中与封装主体接触的散热器的表面积涂覆有金属介质层和绝缘层。

公开(公告)号：US07511366B2

公开(公告)日：2009-03-31

申请号：US11258085

申请日：2005-10-26

Applicant: Yao-Ting Huang ,  Kuang-Lin Lo

Inventor： Yao-Ting Huang ,  Kuang-Lin Lo

IPC: H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-row substrate strip mainly includes a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer includes a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.

Abstract translation: 多排衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。 连接杆用于连接第一基板单元并连接第二基板单元。 脱金属层包括连接杆上的多个流道部分，多个第一栅极部分和多个第二栅极部分。 第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。 电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。

公开(公告)号：US20060091384A1

公开(公告)日：2006-05-04

申请号：US11250526

申请日：2005-10-17

Applicant: Chung-Hsiung Ho ,  Jui-Wen Wang ,  Tien-Ming Shih ,  Kuang-Lin Lo

Inventor： Chung-Hsiung Ho ,  Jui-Wen Wang ,  Tien-Ming Shih ,  Kuang-Lin Lo

IPC: H01L23/58

CPC classification number: G01R1/07335 ,  G01R31/2896 ,  H01L22/32

Abstract: A substrate testing apparatus with full contact configuration. The apparatus includes a jig and a full-contact probe substrate. The jig has a conductive tape disposed thereon for fully electrically connecting a plurality of first connecting pads disposed on an upper surface of a substrate strip. The full-contact probe substrate has a contact surface and includes a plurality of conductive bumps and contact pads. The conductive bumps are disposed on the contact surface, and are used for individually probing a plurality of corresponding second connecting pads disposed on a lower surface of the substrate strip. The contact pads are electrically connected to the conductive bumps. The substrate strip is fully tested by means of the jig and the full-contact probe substrate.

Abstract translation: 具有完全接触配置的基板测试装置。 该装置包括夹具和全接触探针基板。 夹具具有设置在其上的导电胶带，用于完全电连接设置在基板条的上表面上的多个第一连接焊盘。 全接触探针基板具有接触表面并且包括多个导电凸块和接触垫。 导电凸块设置在接触表面上，并且用于单独地探测设置在衬底条的下表面上的多个对应的第二连接焊盘。 接触焊盘电连接到导电凸块。 通过夹具和全接触探针基板对基片条进行全面测试。

公开(公告)号：US06627481B2

公开(公告)日：2003-09-30

申请号：US10056358

申请日：2002-01-25

Applicant: Meng-Tsang Lee ,  Kuang-Lin Lo

Inventor： Meng-Tsang Lee ,  Kuang-Lin Lo

IPC: H01L2144

CPC classification number: H01L21/565 ,  H01L23/49503 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The present invention relates to a method of manufacturing semiconductor packages and products thereof. The method of manufacturing comprises steps of: (a) providing a lead frame which comprises a die pad, a plurality of connecting parts and a plurality of leads, wherein the die pad is lower than the leads and connects the leads through the connecting parts, and wherein the die pad comprises at least one supporting structure to fix the lead frame substantially; (b) mounting a die onto the die pad and electrically connecting the lead frame and die by bonding wires; (c) providing an upper mold and a lower mold, wherein the upper mold and lower mold are located at an upper side and a lower side of the leads, respectively, wherein the supporting structures of the die pad are allowed to be supported on the lower mold, and the leads are allowed to protrude outwards from a mold cavity formed by the upper and lower molds; (d) setting the lead frame in steps (a) and (b) onto the lower mold in step (c) and making the supporting structures of the die pad to be supported on the lower mold and then combining the upper mold to the lower mold; (e) applying an encapsulant into the mold cavity formed by the upper and lower molds; and (f) removing the upper and lower molds after encapsulating.

Abstract translation: 本发明涉及半导体封装的制造方法及其制造方法。 制造方法包括以下步骤：（a）提供引线框架，其包括管芯焊盘，多个连接部件和多个引线，其中管芯焊盘低于引线并且将引线连接到连接部分， 并且其中所述管芯焊盘包括至少一个支撑结构以基本上固定所述引线框架; （b）将管芯安装在管芯焊盘上，并通过接合线电连接引线框架和管芯; （c）提供上模具和下模具，其中上模具和下模具分别位于引线的上侧和下侧，其中模片垫的支撑结构被允许支撑在 下模，允许引线从由上模和下模形成的模腔向外突出; （d）在步骤（c）中将步骤（a）和（b）中的引线框架设置在下模上，并使模片垫的支撑结构支撑在下模上，然后将上模与下模 模子; （e）将密封剂施加到由上模和下模形成的模腔中; 和（f）在封装之后去除上模和下模。

公开(公告)号：US6118176A

公开(公告)日：2000-09-12

申请号：US298848

申请日：1999-04-26

Applicant: Su Tao ,  Kuang-Lin Lo ,  Kuang-Chun Chou ,  Shih-Chih Chen

Inventor： Su Tao ,  Kuang-Lin Lo ,  Kuang-Chun Chou ,  Shih-Chih Chen

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/32 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48992 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107

Abstract: A stacked chip assembly generally includes a first chip, a second chip and a lead frame. The lower surface of the first chip is pasted onto the lower surface of the second chip by an adhesive film so as to form a stacked chip body. The stacked chip body is disposed on the lead frame. Bonding pads of the upper surface of the first chip are interconnected to the upper surface of the inner leads of the lead frame by bonding wires. Bonding pads of the upper surface of the second chip are interconnected to the lower surface of the inner leads of the lead frame by bonding wires. Therefore, the first chip and the second chip are simultaneously interconnected to an external circuit devices through the lead frame.

Abstract translation: 堆叠式芯片组件通常包括第一芯片，第二芯片和引线框架。 第一芯片的下表面通过粘合剂膜粘贴到第二芯片的下表面上，以形成堆叠芯片体。 堆叠的芯片体设置在引线框架上。 第一芯片的上表面的接合焊盘通过接合线互连到引线框架的内引线的上表面。 第二芯片的上表面的接合焊盘通过接合线互连到引线框架的内引线的下表面。 因此，第一芯片和第二芯片通过引线框架同时与外部电路器件互连。

公开(公告)号：US20070087480A1

公开(公告)日：2007-04-19

申请号：US11613195

申请日：2006-12-20

Applicant: Su TAO ,  Kuang-Lin Lo ,  Tsung-Sheng Lee ,  Yaw-Yuh Yang ,  Yuan-Kai Tao

Inventor： Su TAO ,  Kuang-Lin Lo ,  Tsung-Sheng Lee ,  Yaw-Yuh Yang ,  Yuan-Kai Tao

IPC: H01L21/78

CPC classification number: H01L24/97 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. A molding compound is formed to cover the semiconductor chip, the substrate, the top surface and the bottom surface of the stiffener. Afterwards, a singulation step is performed to cut the molding compound, the substrate and the stiffener.

Abstract translation: 本发明涉及一种制造半导体芯片封装结构的方法，包括以下步骤。 提供基板。 将多个芯片组装到基板上并与基板电连接。 加强件组装在基底上，并且加强件具有面向基底的顶表面和底表面。 形成模塑料以覆盖加强件的半导体芯片，基板，顶表面和底表面。 然后，进行切割步骤以切割模塑料，基材和加强件。

公开(公告)号：US06942478B2

公开(公告)日：2005-09-13

申请号：US10268161

申请日：2002-10-10

Applicant: Meng-Tsang Lee ,  Kuang-Lin Lo

Inventor： Meng-Tsang Lee ,  Kuang-Lin Lo

IPC: B29C45/14 ,  B29C45/20 ,  B29C45/27 ,  B29C45/37 ,  H01L23/28

CPC classification number: B29C45/372 ,  B29C45/14655 ,  B29C45/2701

Abstract: The present invention relates to a packaging mold with electrostatic discharge protection comprising a pot block and at least one receiver. The pot block comprises a plurality of pots and runners. Each of the pots branches and connects the runners for injecting molding compound into the runners through the pots. The receiver for supporting a plurality of substrate plates connects the runners for receiving the molding compound from the runners to package the dice on the substrate plates. Each receiver comprises a receiving surface contacting the substrate plate; wherein the receiving surface is roughened to reduce static electric charges generated when separating the substrate plates and the packaging mold. Additionally, the surfaces of the runners are roughened to reduce static electric charges generated in the runners when separating the molding compound and the runners. It prevents the dice packaged from damage due to static electric charges to raise the yield rate of semiconductor package products thereby.

Abstract translation: 本发明涉及一种具有静电放电保护的包装模具，其包括一个罐块和至少一个接收器。 罐块包括多个盆和流道。 每个花盆分支并连接浇道，用于通过盆将浇注料浇注到浇道中。 用于支撑多个基板的接收器连接用于从浇道接收模制化合物的流道，以将模具封装在基板上。 每个接收器包括接触基板的接收表面; 其中所述接收表面被粗糙化以减少在分离所述基板和所述包装模具时产生的静电。 此外，当分离模制化合物和流道时，滑动件的表面被粗糙化以减少流道中产生的静电荷。 它防止由于静电导致包装的骰子损坏，从而提高半导体封装产品的成品率。

公开(公告)号：US6163076A

公开(公告)日：2000-12-19

申请号：US325382

申请日：1999-06-04

Applicant: Chun-Chi Lee ,  Kuang-Lin Lo ,  Kuang-Chwn Chou ,  Shih-Chih Chen

Inventor： Chun-Chi Lee ,  Kuang-Lin Lo ,  Kuang-Chwn Chou ,  Shih-Chih Chen

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49805 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A stacked structure of a semiconductor package mainly comprises a first chip, a second chip, a substrate and a lead frame. The first chip and the second chip are attached on the surface of the substrate by a plurality of solder bumps by means of flipchip bonding. Then, the first chip, the second chip and the substrate form a stacked structure. A plurality of plugs of the substrate is provided along an edge of the substrate so as to attach to a plurality of receptacles of the lead frame to form a semiconductor device. The plugs are attached to the receptacles of the lead frame by silver paste to form a semiconductor device in such a way that the first chip and the second chip electrically connect to the lead frame. In addition, the lead frame is bent to form a plurality of fingers, which is placed in a space that is formed by a sidewall of the chip and a surface of the substrate while it is assembled. An encapsulant covers the stacked structure, then the fingers are exposed on the surface of the encapsulant, so that the first chip and the second chip can be operated by means of the fingers.

Abstract translation: 半导体封装的堆叠结构主要包括第一芯片，第二芯片，基板和引线框架。 第一芯片和第二芯片通过倒装芯片接合通过多个焊料凸块附接在基板的表面上。 然后，第一芯片，第二芯片和基板形成堆叠结构。 沿着基板的边缘设置多个基板插头，以便连接到引线框架的多个插座以形成半导体器件。 插头通过银膏附接到引线框架的插座以形成半导体器件，使得第一芯片和第二芯片电连接到引线框架。 此外，引线框架弯曲以形成多个指状物，其被放置在由芯片的侧壁和基板的表面组装在其中的表面形成的空间中。 密封剂覆盖堆叠结构，然后将指状物暴露在密封剂的表面上，使得第一芯片和第二芯片可以通过手指操作。