公开(公告)号：US07863110B2

公开(公告)日：2011-01-04

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L21/332 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：USD610878S1

公开(公告)日：2010-03-02

申请号：US29337809

申请日：2009-05-29

Applicant: Kwang-Tae Kim

Designer： Kwang-Tae Kim

公开(公告)号：US20080132014A1

公开(公告)日：2008-06-05

申请号：US12012593

申请日：2008-02-04

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US20080093701A1

公开(公告)日：2008-04-24

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L29/00 ,  H01L21/761

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：US08984629B2

公开(公告)日：2015-03-17

申请号：US13148177

申请日：2010-02-03

Applicant: Kwang Tae Kim ,  Yongseok Hwang

Inventor： Kwang Tae Kim ,  Yongseok Hwang

IPC: G06F21/00 ,  G06F21/53 ,  H04L29/06 ,  G06F21/55 ,  G06F21/50

CPC classification number: G06F21/53 ,  G06F21/50 ,  G06F21/55 ,  H04L63/1441

Abstract: In an apparatus and method for protecting resources of a computing system from a malicious code by selective virtualization, at least a part of the resources is classified as compulsory resources for executing a program on the computing system. When a vulnerable program executed in a separate space attempts to access one of the compulsory resources, an operating system level virtualization is performed. Further, when the vulnerable program attempts to access one of the resources of the computing system which is other than the compulsory resources, the vulnerable program is permitted to access a modified resource which is generated by modifying content of the resource.

Abstract translation: 在通过选择性虚拟化来保护计算系统的资源免受恶意代码的装置和方法中，资源的至少一部分被分类为用于在计算系统上执行程序的强制资源。 当在单独空间中执行的易受攻击的程序试图访问其中一个强制资源时，将执行操作系统级虚拟化。 此外，当易受攻击的程序试图访问除强制资源之外的其中一个计算系统的资源时，易受攻击的程序被允许访问通过修改资源的内容产生的修改的资源。

公开(公告)号：US20120331522A1

公开(公告)日：2012-12-27

申请号：US13582609

申请日：2011-03-04

Applicant: Heean Park ,  Kyung Wan Kang ,  Kwang Tae Kim

Inventor： Heean Park ,  Kyung Wan Kang ,  Kwang Tae Kim

IPC: G06F21/20 ,  G06F15/16

CPC classification number: G06F9/45533 ,  G06F9/468

Abstract: A system for logically separating a server using client virtualization includes a client terminal including a virtual environment generation unit for generating a virtual environment, and a virtualized server including a local storage unit, an authentication server for performing authentication on the client terminal when a request for access to the local storage unit is received from a process executed in the virtual environment, and a virtualization filter drier for allowing or blocking the access request to the local storage unit based on the authentication result of the client terminal. The client terminal further includes a virtualization filter drives for transmitting the access request from the process executed in the virtual environment to the local storage unit, and blocking the access request from the process without being made through the virtual environment to the local storage unit.

Abstract translation: 用于使用客户端虚拟化来逻辑地分离服务器的系统包括：客户终端，其包括用于生成虚拟环境的虚拟环境生成单元，以及包括本地存储单元的虚拟化服务器，用于在客户端终端执行认证时， 从虚拟环境中执行的处理接收对本地存储单元的访问，以及虚拟化过滤器干燥器，用于基于客户终端的认证结果来允许或阻止对本地存储单元的访问请求。 客户终端还包括虚拟化过滤器驱动器，用于将从虚拟环境中执行的进程的访问请求发送到本地存储单元，以及阻止来自进程的访问请求而不通过虚拟环境进行到本地存储单元。

公开(公告)号：US07588983B2

公开(公告)日：2009-09-15

申请号：US12012593

申请日：2008-02-04

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US07429511B2

公开(公告)日：2008-09-30

申请号：US11171706

申请日：2005-06-30

Applicant: Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

Inventor： Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  G11C16/0433 ,  H01L27/11524

Abstract: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern to re-flow the re-flowable material layer pattern, removing the second insulating layer and the first insulating layer to expose the substrate, and forming a tunneling insulating layer.

Abstract translation: 提供一种形成尺寸小于通过光刻工艺的分辨率获得的尺寸的隧道绝缘层的方法。 该方法包括在基板上形成第一绝缘层和第二绝缘层的步骤，形成可再流动的材料层图案以再流动可再流动的材料层图案，去除第二绝缘层和第一绝缘层 露出基板，形成隧道绝缘层。

公开(公告)号：US20060006453A1

公开(公告)日：2006-01-12

申请号：US11099658

申请日：2005-04-06

Applicant: Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

Inventor： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US5302459A

公开(公告)日：1994-04-12

申请号：US920710

申请日：1992-07-28

Applicant: Kwang-Tae Kim ,  Ik-Sung Kim ,  Choon-Young Kim

Inventor： Kwang-Tae Kim ,  Ik-Sung Kim ,  Choon-Young Kim

IPC: B29C55/12 ,  B06B1/02 ,  B29C55/02 ,  B29K67/00 ,  B29L7/00 ,  B29L9/00 ,  C08J7/04 ,  C08L83/04 ,  C09D5/00 ,  C09D5/02 ,  C09D133/04 ,  C09D133/06 ,  C09D183/04 ,  C09D183/06 ,  B32B9/04

CPC classification number: C08J7/047 ,  B29C55/026 ,  C09D133/06 ,  B06B2201/56 ,  B29K2067/00 ,  C08J2367/02 ,  C08J2433/00 ,  C08L83/04 ,  Y10T428/31663 ,  Y10T428/31797

Abstract: A method for preparation of a biaxially stretched polyester film with good slip and release properties comprising coating an acrylic resin-based aqueous resin compound, which is derived from adding an amino-modified silicone compound having the structural formula (1), a waxy additive and inert inorganic particles to an acrylic resin, on at least one surface of a mono-axially stretched polyester film, drying the polyester film coated with the aqueous resin compound, mono-axially stretching the dried polyester film in a direction perpendicular to that of the previous mono-axial stretching and heat-treating the stretched polyester film: ##STR1## wherein R' is a hydroxyl group, a methyl or an ethyl; R" is a hydrogen carbide which has 0 to 10 carbon atoms and to which NH or NH.sub.2 is bonded; m is an integer in the range of 5 to 1,000; n is an integer in the range of 100 to 20,000; and n/(m+n)=0.5.

Abstract translation: 一种制备具有良好滑爽和脱模性能的双轴拉伸聚酯薄膜的方法，包括涂布丙烯酸树脂基水性树脂化合物，其衍生自加入具有结构式（1）的氨基改性硅氧烷化合物，蜡状添加剂和 将惰性无机颗粒加入到丙烯酸树脂中，在单轴拉伸聚酯膜的至少一个表面上，干燥涂覆有水性树脂化合物的聚酯膜，沿垂直于先前的方向的方向单轴拉伸干燥的聚酯膜 单轴拉伸和热处理拉伸的聚酯膜：（*化学结构*）（1）其中R'是羟基，甲基或乙基; R“是碳原子数为0〜10并与NH或NH 2键合的碳氢化合物，m为5〜1000的整数，n为100〜20000的整数，n /（ m + n）= 0.5。