公开(公告)号：US07045850B2

公开(公告)日：2006-05-16

申请号：US10844783

申请日：2004-05-13

Applicant: Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

Inventor： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

Abstract translation: 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050186734A1

公开(公告)日：2005-08-25

申请号：US10786239

申请日：2004-02-24

Applicant: In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

Inventor： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11568 ,  Y10S438/954

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract translation: 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US20050088879A1

公开(公告)日：2005-04-28

申请号：US10971201

申请日：2004-10-21

Applicant: Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

Inventor： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC: H01L27/115 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0425

Abstract: A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

Abstract translation: 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US20050048702A1

公开(公告)日：2005-03-03

申请号：US10953553

申请日：2004-09-30

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/335

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract translation: 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US20090239349A1

公开(公告)日：2009-09-24

申请号：US12476698

申请日：2009-06-02

Applicant: Kwang-Wook Koh ,  Hee-Seog Jeon

Inventor： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC: H01L21/76

CPC classification number: H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract translation: 在非易失性存储器件及其制造方法中，形成在半导体衬底中限定有源区的器件隔离层。 在半导体衬底上形成栅绝缘层和第一导电层。 形成一对堆叠图案，每一个在第一导电层上具有隔间电介质层图案和第二导电层图案。 在堆叠图案之间的第一导电层图案上形成掩模图案，掩模图案与每个堆叠图案间隔开。 使用堆叠图案和掩模图案作为蚀刻掩模来图案化第一导电层。 将杂质离子注入到有源区中以形成一对非易失性存储晶体管和选择晶体管。 所得到的非易失性存储器件包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US07557404B2

公开(公告)日：2009-07-07

申请号：US11704003

申请日：2007-02-08

Applicant: Kwang-Wook Koh ,  Hee-Seog Jeon

Inventor： Kwang-Wook Koh ,  Hee-Seog Jeon

IPC: H01L29/788

CPC classification number: H01L27/11524 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521

Abstract: In a nonvolatile memory device and a method of fabricating the same, the nonvolatile memory device may include a semiconductor substrate having a device isolation layer defining an active region, a pair of nonvolatile memory transistors on the active region, a select transistor disposed between the pair of nonvolatile memory transistors, and floating diffusion regions on the active region between each of the nonvolatile memory transistors and the select transistor. The select transistor may include a gate insulation layer having a thickness and a material that are the same as those of gate insulation layers of the nonvolatile memory transistors. The resulting nonvolatile memory device may include a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract translation: 在非易失性存储器件及其制造方法中，非易失性存储器件可包括具有限定有源区的器件隔离层的半导体衬底，有源区上的一对非易失性存储晶体管，位于该对之间的选择晶体管 的非易失性存储晶体管，以及在每个非易失性存储晶体管和选择晶体管之间的有源区上的浮动扩散区。 选择晶体管可以包括具有与非易失性存储晶体管的栅极绝缘层相同的厚度和材料的栅极绝缘层。 所得到的非易失性存储器件可以包括包括一对非易失性存储晶体管和选择晶体管的存储单元单元。

公开(公告)号：US20090121280A1

公开(公告)日：2009-05-14

申请号：US12269771

申请日：2008-11-12

Applicant: Kwang-Wook Koh

Inventor： Kwang-Wook Koh

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7887

Abstract: Described are a semiconductor device, methods of forming the semiconductor device and methods of operating the semiconductor device. The semiconductor device includes a gate electrode and laminated charge trap layers interposed between substrates. The methods of forming the semiconductor device include forming a gate stacked structure including insulating layers having a different etching selectivity, forming spaces on sidewalls of the gate stacked structure using an etching selectivity and forming charge trap layers in the spaces. The methods of operating the semiconductor device include programming trap layers by controlling a voltage applied to a gate electrode.

Abstract translation: 描述了半导体器件，形成半导体器件的方法和操作半导体器件的方法。 该半导体器件包括一个栅电极和夹在衬底之间的层叠的电荷陷阱层。 形成半导体器件的方法包括形成包括具有不同蚀刻选择性的绝缘层的栅层叠结构，使用蚀刻选择性在栅层叠结构的侧壁上形成空间，并在空间中形成电荷陷阱层。 操作半导体器件的方法包括通过控制施加到栅电极的电压来编程陷阱层。

公开(公告)号：US07566928B2

公开(公告)日：2009-07-28

申请号：US11269624

申请日：2005-11-09

Applicant: Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

Inventor： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract translation: 字节操作的非易失性半导体存储器件能够一次一个字节地擦除存储的数据。 字节存储单元可以包括1字节存储晶体管的存储单元阵列。 1字节存储晶体管可以沿一个方向布置，每个包括结区域和形成在有源区域中的沟道区域。 字节存储单元可以包括字节选择晶体管。 选择晶体管可以设置在有源区域中并且包括与每个1字节存储晶体管的结直接相邻的结区域。 字节选择晶体管可以布置在垂直于1字节存储晶体管的排列方向的1字节存储晶体管的上方或下方。

公开(公告)号：US07432159B2

公开(公告)日：2008-10-07

申请号：US11242209

申请日：2005-10-03

Applicant: Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

Inventor： Jae-Hwang Kim ,  Seung-Beom Yoon ,  Kwang-Wook Koh ,  Chang-Hun Lee ,  Sung-Ho Kim ,  Sung-Chul Park ,  Ju-Ri Kim

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract translation: EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极， 器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及 隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。 隧道绝缘层在与浮动栅极相邻的一侧对准。

公开(公告)号：US20060208303A1

公开(公告)日：2006-09-21

申请号：US11378505

申请日：2006-03-17

Applicant: Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

Inventor： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

Abstract translation: 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。