公开(公告)号：US07787294B2

公开(公告)日：2010-08-31

申请号：US12031189

申请日：2008-02-14

Applicant: Ming-Chang Kuo ,  Ming-Hsiu Lee

Inventor： Ming-Chang Kuo ,  Ming-Hsiu Lee

IPC: G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0491

Abstract: An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.

Abstract translation: 提供了一种存储器的操作方法。 存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。 在编程存储器期间，选择一列存储单元。 在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线 在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

公开(公告)号：US20100177553A1

公开(公告)日：2010-07-15

申请号：US12488795

申请日：2009-06-22

Applicant: MING-HSIU LEE ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  YU ZHU

Inventor： MING-HSIU LEE ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  YU ZHU

IPC: G11C11/00 ,  H01L47/00 ,  G11C11/34

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.

Abstract translation: 通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立 低电阻状态。 编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路 电极。

公开(公告)号：US20100097851A1

公开(公告)日：2010-04-22

申请号：US12639789

申请日：2009-12-16

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract translation: 编程相变装置的方法包括选择期望的阈值电压（Vth）并将编程脉冲施加到相变装置中的相变材料。 应用编程脉冲包括向相变材料施加一定量的能量以将该材料的至少一部分驱动在熔化能级以上。 施加到相变材料的能量的一部分被允许消散在熔融能级以下。 控制来自相变材料的能量耗散的形状，直到施加到相变材料的能量小于淬火能量水平，以使相变装置具有期望的Vth。 施加到相变材料的能量的剩余部分被允许消散到环境水平。

公开(公告)号：US20100091558A1

公开(公告)日：2010-04-15

申请号：US12249178

申请日：2008-10-10

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: G11C11/00 ,  H01L45/00

CPC classification number: G11C5/063 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C2213/34 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.

Abstract translation: 存储器件包括底部和顶部电极结构以及它们之间的存储单元。 存储单元包括底部和顶部存储器元件以及它们之间的介电元件。 通过介电元件形成较低的电阻传导路径。 电介质元件可以具有外边缘和中心部分，外边缘比中心部分厚。 为了制造存储器件，通过存储器单元施加电脉冲以形成穿过介质元件的传导路径。 可以通过氧化存储单元的外表面来形成钝化元件，该外表面也可以增大电介质元件的外边缘。

公开(公告)号：US07589368B2

公开(公告)日：2009-09-15

申请号：US11385061

申请日：2006-03-21

Applicant: Ming Hsiu Lee

Inventor： Ming Hsiu Lee

IPC: H01L29/72

CPC classification number: G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

Abstract: Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the memory cells and providing gate regions of the memory cells. Additionally, a first pair of bit lines cross under the two word lines and providing source and drain regions to the first layer of the two layers of the memory arrays, and a second pair of bit lines cross over the two word lines and providing source and drain regions to the second layer of the two layers of the memory arrays. A first set of channel regions are disposed between the source and drain regions to the first layer of the two layers of the memory arrays, and a second set of channel regions are disposed between the source and drain regions to the second layer of the two layers of the memory arrays. In addition, charge storage regions are provided with each of them disposed between a corresponding word line and a corresponding channel region.

Abstract translation: 公开了存储器件。 存储器件的一个示例可以包括每层包含至少四个存储器单元的两层存储器阵列。 特别地，存储器件包括通常由存储器阵列的两层共享的两条字线，字线与存储器单元耦合并提供存储器单元的栅极区。 此外，第一对位线在两个字线之下交叉并且向存储器阵列的两个层的第一层提供源极和漏极区域，并且第二对位线在两个字线上交叉并且提供源极和 漏极区域到存储器阵列的两层的第二层。 第一组沟道区域设置在源极和漏极区之间到存储器阵列的两个层的第一层，并且第二组沟道区设置在源极和漏极区之间到两层的第二层 的存储器阵列。 此外，电荷存储区域设置有它们中的每一个布置在对应的字线和相应的通道区域之间。

公开(公告)号：US20090207658A1

公开(公告)日：2009-08-20

申请号：US12169155

申请日：2008-07-08

Applicant: Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-I Wu

Inventor： Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-I Wu

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0416 ,  G11C16/10 ,  G11C16/14

Abstract: An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array

Abstract translation: 提供了一种存储器阵列的操作方法。 操作方法包括执行编程操作。 通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时编程存储器阵列中的多个选择的存储器单元

公开(公告)号：US20090207656A1

公开(公告)日：2009-08-20

申请号：US12031189

申请日：2008-02-14

Applicant: Ming-Chang Kuo ,  Ming-Hsiu Lee

Inventor： Ming-Chang Kuo ,  Ming-Hsiu Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0491

Abstract: An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.

Abstract translation: 提供了一种存储器的操作方法。 存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。 在编程存储器期间，选择一列存储单元。 在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线 在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

公开(公告)号：US07554873B2

公开(公告)日：2009-06-30

申请号：US11385360

申请日：2006-03-21

Applicant: Ming Hsiu Lee ,  Yen Hao Shih

Inventor： Ming Hsiu Lee ,  Yen Hao Shih

IPC: G11C8/00

CPC classification number: G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a plurality of word lines and bit lines coupled to the memory cells in each plane, and at least one transistor to select at least one of the memory arrays.

Abstract translation: 存储器件包括存储器阵列的多个平面，每个存储器阵列包括多个存储器单元。 存储器件还包括耦合到每个平面中的存储器单元的多个字线和位线，以及至少一个用于选择存储器阵列中的至少一个的晶体管。

公开(公告)号：US20090101966A1

公开(公告)日：2009-04-23

申请号：US12314881

申请日：2008-12-18

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: H01L29/792

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

公开(公告)号：US20080084762A1

公开(公告)日：2008-04-10

申请号：US11601710

申请日：2006-11-20

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。