公开(公告)号：US20060240635A1

公开(公告)日：2006-10-26

申请号：US11113509

申请日：2005-04-25

Applicant: Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

Inventor： Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

Abstract: Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.

Abstract translation: 公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。 一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420.方法300还包括在周边区域314上形成314栅极电介质层426 406，在芯区域402中的多层介电 - 电荷俘获 - 电介质堆叠层420和周边区域406中的栅极电介质426之间形成316第一多晶硅层428，然后同时形成318隔离沟槽438 在核心区域404和外围区域406中的衬底408中。此后，隔离沟槽用介电材料446填充326，第二多晶硅层452形成为332o 形成第一多晶硅层428和填充沟槽438，形成自对准STI结构446.方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少外围栅极氧化物的稀化和 ONO在STI边缘，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

公开(公告)号：US20060216888A1

公开(公告)日：2006-09-28

申请号：US11086310

申请日：2005-03-23

Applicant: Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

Inventor： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

公开(公告)号：US07071538B1

公开(公告)日：2006-07-04

申请号：US11008263

申请日：2004-12-10

Applicant: Hidehiko Shiraiwa ,  Harpreet K. Sachar ,  Mark Randolph ,  Wei Zheng

Inventor： Hidehiko Shiraiwa ,  Harpreet K. Sachar ,  Mark Randolph ,  Wei Zheng

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/3162 ,  H01L21/31662 ,  H01L29/518

Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

Abstract translation: 半导体器件包括还包括源极，漏极和沟道区的衬底。 该器件还可以包括形成在衬底上的底部氧化物层，形成在底部氧化物层上的电荷存储层和在电荷存储层上热生长的蒸汽氧化物层。 该装置还可以包括形成在蒸汽氧化物层上的氧化铝层和形成在氧化铝层上的栅电极。

公开(公告)号：US07003464B2

公开(公告)日：2006-02-21

申请号：US10339067

申请日：2003-01-09

Applicant: James Ferrans ,  Jonathan Engelsma ,  Michael Pearce ,  Mark Randolph ,  Jerome Vogedes

Inventor： James Ferrans ,  Jonathan Engelsma ,  Michael Pearce ,  Mark Randolph ,  Jerome Vogedes

IPC: G10L21/00

CPC classification number: H04M1/72561 ,  G10L15/26 ,  H04M3/4938 ,  H04M2207/40 ,  H04M2250/74

Abstract: A voice browser dialog enabler for multimodal dialog uses a multimodal markup document with fields have markup-based forms associated with each field and defining fragments. A voice browser driver resides on a communication device and provides the fragments and identifiers that identify the fragments. A voice browser implementation resides on a remote voice server and receives the fragments from the driver and downloads a plurality of speech grammars. Input speech is matched against those speech grammars associated with the corresponding identifiers received in a recognition request from the voice browser driver.

Abstract translation: 用于多模式对话框的语音浏览器对话框启用程序使用多模式标记文档，其中字段具有与每个字段相关联的基于标记的表单并定义片段。 语音浏览器驱动程序驻留在通信设备上，并提供标识片段的片段和标识符。 语音浏览器实现驻留在远程语音服务器上，并从驱动程序接收片段并下载多个语音语法。 输入语音与来自语音浏览器驱动程序的识别请求中接收到的相应标识符相关联的那些语音语法相匹配。

公开(公告)号：US20050250278A1

公开(公告)日：2005-11-10

申请号：US10839614

申请日：2004-05-05

Applicant: Mark Randolph

Inventor： Mark Randolph

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8244 ,  H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11517 ,  H01L27/11568

Abstract: Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.

Abstract translation: 提出了用于在制造期间保护闪存字线和存储器单元免于与处理相关的充电的方法和结构。 在掺杂多晶硅字线的端部形成未掺杂的多晶硅，以产生电阻器，通过该电阻将工艺电荷放电到与衬底耦合的掺杂多晶硅放电结构。 字线，电阻器和放电结构可以形成为整体图案化多晶硅结构，其中字线和放电部分被选择性地掺杂为导电的，并且电阻器部分基本上未被掺杂以提供足够高的电阻以允许在 同时在制造期间提供用于处理相关充电的放电路径。

公开(公告)号：US20050077567A1

公开(公告)日：2005-04-14

申请号：US10685044

申请日：2003-10-14

Applicant: Mark Randolph ,  Sameer Haddad ,  Timothy Thurgate ,  Richard Fastow

Inventor： Mark Randolph ,  Sameer Haddad ,  Timothy Thurgate ,  Richard Fastow

IPC: G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

Abstract translation: 存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。 存储单元布置成多行和多列。 每列存储单元包括多个交替沟道区和源极/漏极区。 导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。 另一个源/漏区位于与该列相邻的第二列中。 导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。 多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

公开(公告)号：US06666446B2

公开(公告)日：2003-12-23

申请号：US09880407

申请日：2001-06-13

Applicant: Glenn Gaarder ,  Mark Randolph Marrs

Inventor： Glenn Gaarder ,  Mark Randolph Marrs

IPC: B65H500

CPC classification number: B65H3/0684 ,  B65H3/0669 ,  B65H2402/60 ,  B65H2403/42 ,  B65H2404/142 ,  B65H2601/324

Abstract: A replaceable roller bogie for a single sheet feeder includes pre-feed and separation rollers mounted on a frame which also has a frame positioning lever thereon. Roller drive gears are mounted between spaced plates on the frame and include a pre-feed roller clutch gear with elastomeric teeth which is mounted in slots on the frame which limit motion travel of the clutch gear to prevent over engagement of gear teeth on the clutch gear with gear teeth on the pre-feed roller drive gear. The replaceable bogie is pivotally supported on the sheet feeder and held in place by a manually operable release and latch mechanism.

公开(公告)号：US06627243B2

公开(公告)日：2003-09-30

申请号：US09756930

申请日：2001-01-10

Applicant: George Cherian ,  Mark Randolph Jacobson ,  Dharam Vir Vadehra

Inventor： George Cherian ,  Mark Randolph Jacobson ,  Dharam Vir Vadehra

IPC: A23C1300

CPC classification number: A23C13/14 ,  A23L9/20 ,  A23L23/00 ,  A23L29/238 ,  A23L29/27

Abstract: A cream substitute comprising from 5% to 40% by weight of butter, from about 0.25% to about 5% by weight of a thickening agent, and about 0.25% to about 4% of a food protein, based on the total weight of the cream substitute, together with a sufficient amount of water to total 100% by weight, and, optionally, from about 0.05% to about 2% by weight of a food acceptable acid.

Abstract translation: 基于总重量的奶油替代物，其包含5重量％至40重量％的黄油，约0.25重量％至约5重量％的增稠剂和约0.25重量％至约4重量％的食品蛋白质 奶油代用品，以及足够量的水至100重量％，以及任选的约0.05重量％至约2重量％的可食用酸。

公开(公告)号：US06465303B1

公开(公告)日：2002-10-15

申请号：US09885490

申请日：2001-06-20

Applicant: Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

Inventor： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

Abstract translation: 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

公开(公告)号：US06168637A

公开(公告)日：2001-01-02

申请号：US08991322

申请日：1997-12-16

Applicant: Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

Inventor： Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

IPC: H01L218247

CPC classification number: H01L27/11521 ,  Y10T29/41

Abstract: A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.

Abstract translation: 公开了一种用于在半导体上提供闪存单元的方法和系统。 在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。 在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。