公开(公告)号：US20050077567A1

公开(公告)日：2005-04-14

申请号：US10685044

申请日：2003-10-14

申请人： Mark Randolph ,  Sameer Haddad ,  Timothy Thurgate ,  Richard Fastow

发明人： Mark Randolph ,  Sameer Haddad ,  Timothy Thurgate ,  Richard Fastow

IPC分类号： G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

摘要翻译： 存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。 存储单元布置成多行和多列。 每列存储单元包括多个交替沟道区和源极/漏极区。 导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。 另一个源/漏区位于与该列相邻的第二列中。 导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。 多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

公开(公告)号：US20050153508A1

公开(公告)日：2005-07-14

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

发明人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L2976

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US07176113B1

公开(公告)日：2007-02-13

申请号：US10862636

申请日：2004-06-07

申请人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

发明人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/425

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。 轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。 因此，可以在相同或更小的区域内形成或“包装”更多的装置。

公开(公告)号：US06934190B1

公开(公告)日：2005-08-23

申请号：US10863933

申请日：2004-06-09

申请人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

发明人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

摘要翻译： 提供了包括具有一定范围值的编程的双位存储器件的操作方法。 本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。 该范围与存储器件内的各个双位存储单元的通道长度有关。 为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。 此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。 然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US07626869B2

公开(公告)日：2009-12-01

申请号：US11745327

申请日：2007-05-07

申请人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

发明人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

摘要翻译： 同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。 然而，其他字线不受影响，因为它们在联系人旁边。 因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

公开(公告)号：US06770938B1

公开(公告)日：2004-08-03

申请号：US10050394

申请日：2002-01-16

申请人： Michael Fliesler ,  Mark Ramsbey ,  Mark Randolph ,  Ian Morgan ,  Timothy Thurgate ,  Paohua Kuo ,  David M. Rogers

发明人： Michael Fliesler ,  Mark Ramsbey ,  Mark Randolph ,  Ian Morgan ,  Timothy Thurgate ,  Paohua Kuo ,  David M. Rogers

IPC分类号： H01L2362

CPC分类号： H01L27/0255

摘要： An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

摘要翻译： 为集成电路提供ESD保护装置。 ESD保护装置包括由二极管形成并耦合在第一电源VCC和第二电源VSS之间的电源钳位装置。 还提供一种输入保护装置，其由耦合在输入焊盘和第一电源之间的二极管和耦合在输入焊盘和第二电源之间的第二二极管形成。 二极管具有调整的反向击穿电压，其高于用于为驱动集成电路的核心内的电路的外围电路供电的电压源VCC。 调整的反向击穿电压也低于在外围电路中使用的栅极氧化物层的击穿电压。

公开(公告)号：US20080279014A1

公开(公告)日：2008-11-13

申请号：US11745327

申请日：2007-05-07

申请人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

发明人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

摘要翻译： 同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。 然而，其他字线不受影响，因为它们在联系人旁边。 因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

公开(公告)号：US09732321B2

公开(公告)日：2017-08-15

申请号：US13028725

申请日：2011-02-16

申请人： Erik Bassett ,  Mack Cheney ,  Theresa Hadlock ,  Irina Pomerantseva ,  Mark Randolph ,  Cathryn Sundback ,  Joseph Vacanti

发明人： Erik Bassett ,  Mack Cheney ,  Theresa Hadlock ,  Irina Pomerantseva ,  Mark Randolph ,  Cathryn Sundback ,  Joseph Vacanti

IPC分类号： A61F2/02 ,  C12N5/077 ,  A61L27/04 ,  A61L27/24 ,  A61L27/50 ,  C12N5/0775

CPC分类号： C12N5/0655 ,  A61L27/04 ,  A61L27/24 ,  A61L27/50 ,  C12N5/0663 ,  C12N2501/15 ,  C12N2502/1317 ,  C12N2533/54

摘要： The present invention provides for compositions and constructs for craniofacial reconstruction implants, and methods for making and using same. Specific embodiments provide for a biocompatible scaffold having an auricular shape and a permanent bendable framework within the scaffold, wherein the permanent bendable framework allows deformation and return to pre-deformation shape, and thus maintains the auricular shape of the scaffold.