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    Integrated circuit interconnect
    12.
    发明授权
    Integrated circuit interconnect 有权
    集成电路互连

    公开(公告)号：US07332811B2

    公开(公告)日：2008-02-19

    申请号：US11427746

    申请日：2006-06-29

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L23/40 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Method of trench isolation using spacers to form isolation trenches with protected corners
    13.
    发明授权
    Method of trench isolation using spacers to form isolation trenches with protected corners 失效
    使用间隔件形成具有受保护角的隔离沟槽的沟槽隔离方法

    公开(公告)号：US5966615A

    公开(公告)日：1999-10-12

    申请号：US25078

    申请日：1998-02-17

    申请人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    发明人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76232 ,  Y10S438/978

    摘要： A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

    摘要翻译： 用于隔离半导体衬底上的有源器件的沟槽，通过产生具有周边边缘的沟槽，并在沟槽中设置隔离材料形成。 隔离材料在沟槽的周缘延伸，从而覆盖围绕沟槽的衬底的至少一部分，并且基本上限制了设置在衬底上的有源器件的泄漏。

    Method of making a resistor
    14.
    发明授权
    Method of making a resistor 失效
    制作电阻的方法

    公开(公告)号：US5635418A

    公开(公告)日：1997-06-03

    申请号：US409505

    申请日：1995-03-23

    申请人： Martin C. Roberts

    发明人： Martin C. Roberts

    IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L28/20 ,  H01L27/0802 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/979

    摘要： A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.

    摘要翻译： 从半导体材料形成电阻器的半导体处理方法包括：a）提供与电阻器进行电连接的节点; b）在节点外部提供第一电绝缘材料; c）在所述节点外部的所述第一电绝缘材料中提供暴露的垂直侧壁; d）在所述第一材料的外部和所述第一材料垂直侧壁上方提供第二电绝缘材料，所述第一和第二材料可相对于彼此选择性地蚀刻; e）相对于所述第一材料选择性地各向异性地蚀刻所述第二材料，以在所述第一材料垂直侧壁上方形成基本上垂直延伸的侧壁隔离物，并且向外暴露所述邻近所述侧壁间隔物的所述第一材料，所述间隔件具有内表面和外表面; f）相对于第二材料选择性地蚀刻第一材料以向外暴露间隔件外表面的至少一部分; g）在所述暴露的外隔离物表面上并在所述内间隔件表面上提供半导体材料的保形层，所述共形层与所述节点形成电连接; 以及h）将所述保形层图案化成所需的电阻器形状。 公开了SRAM和其它集成电路的集成电路。

    Spacers used to form isolation trenches with improved corners
    15.
    发明授权
    Spacers used to form isolation trenches with improved corners 失效
    隔板用于形成具有改进拐角的隔离沟槽

    公开(公告)号：US5433794A

    公开(公告)日：1995-07-18

    申请号：US988613

    申请日：1992-12-10

    申请人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    发明人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    IPC分类号： H01L21/762 ,  H01L49/00

    CPC分类号： H01L21/76232 ,  Y10S438/978

    摘要： A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

    摘要翻译： 用于隔离半导体衬底上的有源器件的沟槽，通过产生具有周边边缘的沟槽，并在沟槽中设置隔离材料形成。 隔离材料在沟槽的周缘延伸，从而覆盖围绕沟槽的衬底的至少一部分，并且基本上限制了设置在衬底上的有源器件的泄漏。

    Semiconductor wafer processing method of forming channel stops and method of forming SRAM circuitry
    16.
    发明授权
    Semiconductor wafer processing method of forming channel stops and method of forming SRAM circuitry 失效
    形成通道停止的半导体晶片处理方法和形成SRAM电路的方法

    公开(公告)号：US5240874A

    公开(公告)日：1993-08-31

    申请号：US963725

    申请日：1992-10-20

    申请人： Martin C. Roberts

    发明人： Martin C. Roberts

    IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L27/11 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/823481

    摘要： A semiconductor device isolation method of forming a channel stop in a semiconductor wafer comprises: a) selectively forming field oxide on a semiconductor wafer surface, the field oxide having a bird's beak region and a non-bird's beak region, the bird's beak region laterally extending into a desired region on the wafer; b) masking the bird's beak region and desired region; c) with the masking in place, ion implanting a selected material into the wafer through the non-bird's beak region of the field oxide to define a channel stop implant in the wafer under the non-bird's beak region of the field oxide, such non-bird's beak region implant being conducted at an implant angle along the bird's beak which is less than about 10.degree. from perpendicular relative to the wafer surface; and d) with the masking in place, ion implanting a selected material into the wafer through the bird's beak region of the field oxide to define a channel stop implant in the wafer under and along the bird's beak region of the field oxide, such bird's beak region implant being conducted at an implant angle along the bird' s beak region which is greater than about 10.degree. and less than about 40.degree. from perpendicular relative to the wafer surface.

    摘要翻译： 在半导体晶片中形成通道阻挡的半导体器件隔离方法包括：a）在半导体晶片表面上选择性地形成场氧化物，所述场氧化物具有鸟喙区域和非鸟喙区域，所述鸟喙区域横向延伸 进入晶片上的期望区域; b）遮蔽鸟的喙区域和所需区域; c）在屏蔽位置的情况下，通过场氧化物的非鸟嘴区将离子注入到晶片中，以在场氧化物的非鸟喙区域之下的晶片中限定通道停止注入， ird的喙区域植入物沿着鸟嘴的植入角度进行，该距离离垂直于晶片表面小于约10°; 并且d）将掩蔽置于适当位置，通过场氧化物的鸟嘴区将离子注入到晶片中，以便在场氧化物的鸟喙区域下方和沿着晶状体氧化物的鸟嘴区域限定通道停止植入物，这样的鸟嘴 区域植入物以沿着相对于晶片表面的垂直方向大于约10°且小于约40°的鸟嘴区域的植入角度进行。

    Integrated circuit using a dual poly process
    17.
    发明授权
    Integrated circuit using a dual poly process 有权
    集成电路使用双重多工艺

    公开(公告)号：US07160801B2

    公开(公告)日：2007-01-09

    申请号：US09745780

    申请日：2000-12-21

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Isolation structure of a shallow semiconductor device trench
    18.
    发明授权
    Isolation structure of a shallow semiconductor device trench 失效
    浅半导体器件沟槽的隔离结构

    公开(公告)号：US5868870A

    公开(公告)日：1999-02-09

    申请号：US798968

    申请日：1997-02-11

    申请人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    发明人： Pierre C. Fazan ,  Martin C. Roberts ,  Gurtej S. Sandhu

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76232 ,  Y10S438/978

    摘要： A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

    摘要翻译： 用于隔离半导体衬底上的有源器件的沟槽，通过产生具有周边边缘的沟槽，并在沟槽中设置隔离材料形成。 隔离材料在沟槽的周缘延伸，从而覆盖围绕沟槽的衬底的至少一部分，并且基本上限制了设置在衬底上的有源器件的泄漏。

    Method for making a fillet for integrated circuit metal plug
    20.
    发明授权
    Method for making a fillet for integrated circuit metal plug 失效
    制造集成电路金属插头圆角的方法

    公开(公告)号：US5387550A

    公开(公告)日：1995-02-07

    申请号：US832349

    申请日：1992-02-07

    申请人： David F. Cheffings ,  Martin C. Roberts

    发明人： David F. Cheffings ,  Martin C. Roberts

    IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L21/76849 ,  H01L21/76877

    摘要： A well in a semiconductor wafer is partially filled by a tungsten plug having an irregular surface. There is an aluminum line exterior of the well for electrically connecting the tungsten plug into an electrical circuit. A doped polysilicon fillet having an irregular surface meshing with the irregular surface of the tungsten plug fills the portion of the well between the plug and line, making a reproducible good electrical connection between the tungsten plug and the aluminum line. The poly fillet is formed by a poly deposit and planarization performed between a tungsten plug overetch and aluminum line deposition.

    摘要翻译： 半导体晶片中的阱部分地由具有不规则表面的钨丝塞填充。 井的铝线外部用于将钨插头电连接到电路中。 具有与钨塞的不规则表面啮合的不规则表面的掺杂多晶硅圆角填充了插塞和线之间的阱部分，从而在钨插头和铝线之间形成可重现的良好的电连接。 多孔圆角由钨丝过孔和铝线沉积之间进行的多晶沉积和平坦化形成。