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    Method for forming an integrated circuit interconnect using a dual poly process
    3.
    发明授权
    Method for forming an integrated circuit interconnect using a dual poly process 失效
    使用双重聚合方法形成集成电路互连的方法

    公开(公告)号：US06740573B2

    公开(公告)日：2004-05-25

    申请号：US08390714

    申请日：1995-02-17

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L213205

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Integrated circuit using a dual poly process
    5.
    发明授权
    Integrated circuit using a dual poly process 有权
    集成电路使用双重多工艺

    公开(公告)号：US07160801B2

    公开(公告)日：2007-01-09

    申请号：US09745780

    申请日：2000-12-21

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Dual poly integrated circuit interconnect
    6.
    发明授权
    Dual poly integrated circuit interconnect 有权
    双聚合集成电路互连

    公开(公告)号：US5923584A

    公开(公告)日：1999-07-13

    申请号：US134005

    申请日：1998-08-14

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  G11C13/00 ,  G11C11/40

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002

    摘要： An electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 覆盖衬底的掩埋接触区域的电互连的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Integrated circuit interconnect
    7.
    发明授权
    Integrated circuit interconnect 有权
    集成电路互连

    公开(公告)号：US07332811B2

    公开(公告)日：2008-02-19

    申请号：US11427746

    申请日：2006-06-29

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L23/40 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Method for forming an integrated circuit interconnect using a dual poly process
    8.
    发明授权
    Method for forming an integrated circuit interconnect using a dual poly process 有权
    使用双重聚合方法形成集成电路互连的方法

    公开(公告)号：US06596632B2

    公开(公告)日：2003-07-22

    申请号：US09805546

    申请日：2001-03-13

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L2144

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

    Method of forming a narrow self-aligned, annular opening in a masking layer
    9.
    发明授权
    Method of forming a narrow self-aligned, annular opening in a masking layer 失效
    在掩模层中形成狭窄的自对准环形开口的方法

    公开(公告)号：US5047117A

    公开(公告)日：1991-09-10

    申请号：US588639

    申请日：1990-09-26

    申请人： Martin C. Roberts

    发明人： Martin C. Roberts

    IPC分类号： H01L21/308 ,  H01L21/762

    CPC分类号： H01L21/76205 ,  H01L21/3086 ,  H01L21/76264 ,  H01L21/76289 ,  Y10S438/947

    摘要： A process for forming within a masking layer a self-aligned annular opening having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography. The process involves the following steps: creation of a mask island using conventional photomasking and etching techniques, the perimeter of said island defining the inner perimeter of the perimetric annular opening; blanket deposition of a spacer layer, the thickness of which is equal to the desired width of the annular opening; a blanket deposition of a thick protective layer that is independently etchable over the spacer layer; planarization of the protection layer to or below the top of the spacer layer; and isotropically etching the exposed spacer layer to form a narrow annular opening exposing the substrate. At this point the exposed substrate may be trenched in order to isolate the area definedd by the island, or it may be fabricated in some other configuration. This method of forming an annular opening within a mask region results in a narrow annular opening that is self-aligned with the mask island and the non-etched spacer layer. Subsequent trench fabrication has the self-alignment features of the narrow annular opening. Both the position and width of the narrow annular opening, and therefore the trench, are highly predictable and the method requires minimum masking steps. The narrowness of the annular opening also maximizes die space.

    摘要翻译： 在掩模层内形成自对准环形开口的方法，其具有基本上比可用光刻的最大分辨率直接产生的空间宽度窄的宽度。 该方法包括以下步骤：使用常规光掩模和蚀刻技术产生掩模岛，所述岛的周界限定周边环形开口的内周边; 间隔层的整体沉积，其厚度等于环形开口的期望宽度; 沉积厚的保护层，其可独立地在间隔层上蚀刻; 将保护层平坦化到间隔层的顶部或之下; 并且各向同性蚀刻暴露的间隔层以形成暴露衬底的窄环形开口。 在这一点上，暴露的衬底可以被沟槽以便隔离由岛限定的区域，或者可以以某种其它构造制造。 在掩模区域内形成环形开口的这种方法导致与掩模岛和未蚀刻的间隔层自对准的窄的环形开口。 随后的沟槽制造具有窄的环形开口的自对准特征。 窄的环形开口的位置和宽度以及因此的沟槽都是高度可预测的，并且该方法需要最小的掩蔽步骤。 环形开口的狭窄也使模具空间最大化。

    Passivation of sidewalls of a word line stack
    10.
    发明授权
    Passivation of sidewalls of a word line stack 有权
    钝化字线堆叠的侧壁

    公开(公告)号：US06198144B1

    公开(公告)日：2001-03-06

    申请号：US09376232

    申请日：1999-08-18

    申请人： Pai-Hung Pan ,  Martin C. Roberts ,  Gurtei S. Sandhu ,  Weimin Li ,  Christopher W. Hill ,  Vishnu K. Agarwal

    发明人： Pai-Hung Pan ,  Martin C. Roberts ,  Gurtei S. Sandhu ,  Weimin Li ,  Christopher W. Hill ,  Vishnu K. Agarwal

    IPC分类号： H01L213205

    CPC分类号： H01L21/28167 ,  H01L21/28061 ,  H01L21/28176 ,  H01L27/10873 ,  H01L29/6653 ,  H01L29/66545

    摘要： A method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls. Subsequently, a reoxidation process is performed with respect to the gate dielectric. By providing the nitride spacers along exposed surfaces of conductive barrier and metal layers of the word line stack, those surfaces can be passivated, thereby preventing or reducing the conversion of those layers to non-conductive compounds during the reoxidation process. At the same time, the nitride spacers can be formed so that they do not interfere with the subsequent reoxidation of the gate dielectric. An integrated circuit having a gate electrode stack with nitride spacers extending along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls is also disclosed.

    摘要翻译： 在晶片上制造集成电路的方法包括在栅极电介质上形成栅极电极堆叠，并且沿着侧壁的最下部分沿着栅电极堆叠的侧壁形成氮化物间隔物。 随后，对栅极电介质进行再氧化处理。 通过在字线堆叠的导电阻挡层和金属层的暴露表面上设置氮化物间隔物，可以钝化那些表面，从而在再氧化过程期间防止或减少这些层向非导电化合物的转化。 同时，可以形成氮化物间隔物，使得它们不干扰栅极电介质的随后的再氧化。 还公开了具有栅极电极堆叠的集成电路，其具有沿着侧壁的侧壁延伸的氮化物间隔物，而不是沿着侧壁的最下部分延伸。