公开(公告)号：US5387550A

公开(公告)日：1995-02-07

申请号：US832349

申请日：1992-02-07

申请人： David F. Cheffings ,  Martin C. Roberts

发明人： David F. Cheffings ,  Martin C. Roberts

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76849 ,  H01L21/76877

摘要： A well in a semiconductor wafer is partially filled by a tungsten plug having an irregular surface. There is an aluminum line exterior of the well for electrically connecting the tungsten plug into an electrical circuit. A doped polysilicon fillet having an irregular surface meshing with the irregular surface of the tungsten plug fills the portion of the well between the plug and line, making a reproducible good electrical connection between the tungsten plug and the aluminum line. The poly fillet is formed by a poly deposit and planarization performed between a tungsten plug overetch and aluminum line deposition.

摘要翻译： 半导体晶片中的阱部分地由具有不规则表面的钨丝塞填充。 井的铝线外部用于将钨插头电连接到电路中。 具有与钨塞的不规则表面啮合的不规则表面的掺杂多晶硅圆角填充了插塞和线之间的阱部分，从而在钨插头和铝线之间形成可重现的良好的电连接。 多孔圆角由钨丝过孔和铝线沉积之间进行的多晶沉积和平坦化形成。

公开(公告)号：US08772848B2

公开(公告)日：2014-07-08

申请号：US13191293

申请日：2011-07-26

申请人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

发明人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

摘要翻译： 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US06740573B2

公开(公告)日：2004-05-25

申请号：US08390714

申请日：1995-02-17

申请人： Martin C. Roberts ,  Sanh D. Tang

发明人： Martin C. Roberts ,  Sanh D. Tang

IPC分类号： H01L213205

CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

公开(公告)号：US06200892B1

公开(公告)日：2001-03-13

申请号：US09135111

申请日：1998-08-17

申请人： Martin C. Roberts ,  Sanh D. Tang

发明人： Martin C. Roberts ,  Sanh D. Tang

IPC分类号： H01L2144

CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

公开(公告)号：US5047117A

公开(公告)日：1991-09-10

申请号：US588639

申请日：1990-09-26

申请人： Martin C. Roberts

发明人： Martin C. Roberts

IPC分类号： H01L21/308 ,  H01L21/762

CPC分类号： H01L21/76205 ,  H01L21/3086 ,  H01L21/76264 ,  H01L21/76289 ,  Y10S438/947

摘要： A process for forming within a masking layer a self-aligned annular opening having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography. The process involves the following steps: creation of a mask island using conventional photomasking and etching techniques, the perimeter of said island defining the inner perimeter of the perimetric annular opening; blanket deposition of a spacer layer, the thickness of which is equal to the desired width of the annular opening; a blanket deposition of a thick protective layer that is independently etchable over the spacer layer; planarization of the protection layer to or below the top of the spacer layer; and isotropically etching the exposed spacer layer to form a narrow annular opening exposing the substrate. At this point the exposed substrate may be trenched in order to isolate the area definedd by the island, or it may be fabricated in some other configuration. This method of forming an annular opening within a mask region results in a narrow annular opening that is self-aligned with the mask island and the non-etched spacer layer. Subsequent trench fabrication has the self-alignment features of the narrow annular opening. Both the position and width of the narrow annular opening, and therefore the trench, are highly predictable and the method requires minimum masking steps. The narrowness of the annular opening also maximizes die space.

摘要翻译： 在掩模层内形成自对准环形开口的方法，其具有基本上比可用光刻的最大分辨率直接产生的空间宽度窄的宽度。 该方法包括以下步骤：使用常规光掩模和蚀刻技术产生掩模岛，所述岛的周界限定周边环形开口的内周边; 间隔层的整体沉积，其厚度等于环形开口的期望宽度; 沉积厚的保护层，其可独立地在间隔层上蚀刻; 将保护层平坦化到间隔层的顶部或之下; 并且各向同性蚀刻暴露的间隔层以形成暴露衬底的窄环形开口。 在这一点上，暴露的衬底可以被沟槽以便隔离由岛限定的区域，或者可以以某种其它构造制造。 在掩模区域内形成环形开口的这种方法导致与掩模岛和未蚀刻的间隔层自对准的窄的环形开口。 随后的沟槽制造具有窄的环形开口的自对准特征。 窄的环形开口的位置和宽度以及因此的沟槽都是高度可预测的，并且该方法需要最小的掩蔽步骤。 环形开口的狭窄也使模具空间最大化。

公开(公告)号：US06596632B2

公开(公告)日：2003-07-22

申请号：US09805546

申请日：2001-03-13

申请人： Martin C. Roberts ,  Sanh D. Tang

发明人： Martin C. Roberts ,  Sanh D. Tang

IPC分类号： H01L2144

CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

公开(公告)号：US06198144B1

公开(公告)日：2001-03-06

申请号：US09376232

申请日：1999-08-18

申请人： Pai-Hung Pan ,  Martin C. Roberts ,  Gurtei S. Sandhu ,  Weimin Li ,  Christopher W. Hill ,  Vishnu K. Agarwal

发明人： Pai-Hung Pan ,  Martin C. Roberts ,  Gurtei S. Sandhu ,  Weimin Li ,  Christopher W. Hill ,  Vishnu K. Agarwal

IPC分类号： H01L213205

CPC分类号： H01L21/28167 ,  H01L21/28061 ,  H01L21/28176 ,  H01L27/10873 ,  H01L29/6653 ,  H01L29/66545

摘要： A method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls. Subsequently, a reoxidation process is performed with respect to the gate dielectric. By providing the nitride spacers along exposed surfaces of conductive barrier and metal layers of the word line stack, those surfaces can be passivated, thereby preventing or reducing the conversion of those layers to non-conductive compounds during the reoxidation process. At the same time, the nitride spacers can be formed so that they do not interfere with the subsequent reoxidation of the gate dielectric. An integrated circuit having a gate electrode stack with nitride spacers extending along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls is also disclosed.

摘要翻译： 在晶片上制造集成电路的方法包括在栅极电介质上形成栅极电极堆叠，并且沿着侧壁的最下部分沿着栅电极堆叠的侧壁形成氮化物间隔物。 随后，对栅极电介质进行再氧化处理。 通过在字线堆叠的导电阻挡层和金属层的暴露表面上设置氮化物间隔物，可以钝化那些表面，从而在再氧化过程期间防止或减少这些层向非导电化合物的转化。 同时，可以形成氮化物间隔物，使得它们不干扰栅极电介质的随后的再氧化。 还公开了具有栅极电极堆叠的集成电路，其具有沿着侧壁的侧壁延伸的氮化物间隔物，而不是沿着侧壁的最下部分延伸。

公开(公告)号：US5376577A

公开(公告)日：1994-12-27

申请号：US268489

申请日：1994-06-30

申请人： Martin C. Roberts ,  Tyler A. Lowrey

发明人： Martin C. Roberts ,  Tyler A. Lowrey

IPC分类号： H01L29/41 ,  H01L21/265 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/10 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L21/768 ,  H01L21/76895

摘要： The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping the sacrificial silicon dioxide layer; growing a gate silicon dioxide layer over the spaced apart areas; depositing a first polysilicon layer over the gate silicon dioxide layer; patterning a buried contact window in the first polysilicon layer, thereby exposing the first N-type diffusion region and re-exposing the field silicon dioxide end portion; depositing a second polysilicon layer superjacent the first polysilicon layer and patterning whereby the first polysilicon layer forms a gate over the gate and the second polysilicon layer makes direct contact to the first N-type diffusion region; wherein the dopants from the patterned doped polysilicon forms a second N-type diffusion region within the first N-type diffusion region.

摘要翻译： 本发明是通过以下步骤形成掩埋触点的静态随机存取存储器制造工艺：在场二氧化硅区域和衬底的间隔开的区域上构图光致抗蚀剂层，从而提供掩埋接触植入窗口以暴露 至少一个间隔开的区域的一部分和相邻的场二氧化硅末端部分; 通过所述埋入式接触窗注入N型掺杂剂，所述注入在所述暴露的间隔开的区域中形成第一N型扩散区并改变所述暴露的场二氧化硅端部的蚀刻速率; 剥离掩模层; 在场二氧化硅区域和支撑硅衬底的间隔开的区域上生长牺牲二氧化硅层，从而使暴露的场二氧化硅端部部分退火并将暴露的场二氧化硅末端部分的蚀刻速率返回到基本相同 蚀刻速率在植入步骤之前; 剥离牺牲二氧化硅层; 在间隔开的区域上生长栅极二氧化硅层; 在栅极二氧化硅层上沉积第一多晶硅层; 在第一多晶硅层中构图掩埋的接触窗，从而暴露第一N型扩散区并再次暴露场二氧化硅端部; 在所述第一多晶硅层之上沉积第二多晶硅层并构图，由此所述第一多晶硅层在所述栅极上形成栅极，并且所述第二多晶硅层与所述第一N型扩散区直接接触; 其中来自图案化掺杂多晶硅的掺杂剂在第一N型扩散区内形成第二N型扩散区。

公开(公告)号：US5064776A

公开(公告)日：1991-11-12

申请号：US592121

申请日：1990-10-03

申请人： Martin C. Roberts

发明人： Martin C. Roberts

IPC分类号： H01L21/74 ,  H01L23/48

CPC分类号： H01L21/743 ,  Y10S148/031 ,  Y10S148/123

摘要： A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure. The migration region extends laterally away from the gate layer to make contact with a remote diffusion region, thereby effecting with the polysilicon interconnect structure the desired buried contact.

摘要翻译： 形成在半导体衬底的表面处的晶体管器件的栅极与形成在远离晶体管器件的衬底的表面中的扩散区域之间的埋入接触。 掩埋触点包括在栅极层和栅极绝缘体成形之后形成的多晶硅互连结构。 多晶硅互连结构通过从栅极层和衬底表面之间的各向同性蚀刻去除栅极绝缘体的位置处接合栅极层的侧边缘和相邻的下表面。 多晶硅互连层还在栅极层的突出边缘下方接触衬底的表面，以形成表面电流通路接口。 在表面电流通路接口下面，通过离子从栅极层通过多晶硅互连结构的热诱导运动形成迁移区域。 迁移区域横向延伸离开栅极层以与远程扩散区域接触，从而通过多晶硅互连结构实现所需的掩埋接触。

公开(公告)号：US07160801B2

公开(公告)日：2007-01-09

申请号：US09745780

申请日：2000-12-21

申请人： Martin C. Roberts ,  Sanh D. Tang

发明人： Martin C. Roberts ,  Sanh D. Tang

IPC分类号： H01L21/4763

CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。