-
11.发明申请PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES 审中-公开具有执行核心部分的处理器以不同的时钟速率运行公开(公告)号：US20120042151A1
公开(公告)日：2012-02-16
申请号：US12879872
申请日：2010-09-10
CPC分类号： G06F9/3842 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。 可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。
-
12.发明申请METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR OR THE LIKE 有权用于在处理器中等待线程优先级的方法和装置公开(公告)号：US20090070562A1
公开(公告)日：2009-03-12
申请号：US12267394
申请日：2008-11-07
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
-
公开(公告)号：US06643747B2
公开(公告)日：2003-11-04
申请号：US09751625
申请日：2000-12-27
IPC分类号： G06F1200
CPC分类号： G06F12/0857
摘要： A request received from a requester to access a processor cache or register file or the like is buffered, by storing requestor identification, request type, address, and a status of the request. This buffered request may be forwarded to the cache if it has the highest priority among a number of buffered requests that also wish to access the cache. The priority is a function of at least the requestor identification, the requester type, and the status of the request. For buffered requests which include a read, the buffered request is deleted after, not before, receiving an indication that the requestor has received the data read from the cache.
-
14.发明授权Processor having execution core sections operating at different clock rates 有权具有执行核心部分以不同时钟速率工作的处理器公开(公告)号：US06256745B1
公开(公告)日：2001-07-03
申请号：US09527065
申请日：2000-03-16
IPC分类号： G06F106
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能比第一执行核心部分慢的I / O环，可选地，第一执行核心部分可以包括其时钟速率在第一和第二执行核心部分之间的时钟速率的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。
-
公开(公告)号：US6018786A
公开(公告)日：2000-01-25
申请号：US956375
申请日：1997-10-23
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/3802 , G06F9/3836
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译： 高速缓冲存储器由数据阵列和控制逻辑构成。 数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。 在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。 通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员 行的逻辑顺序关联。
-
16.发明授权Method and apparatus for designing the layout of a subcircuit in an integrated circuit 失效用于设计集成电路中的分支电路的布局的方法和装置
公开(公告)号：US5351197A
公开(公告)日：1994-09-27
申请号：US824707
申请日：1992-01-21
CPC分类号： G06F17/5068 , H01L27/0207
摘要： A method and apparatus for determining integrated circuit layouts of a random access memory (RAM) from a virtual circuit description and specification of a process technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed in terms of reference points relative to a substrate surface. When the process technology is specified, the relationships among the reference points is determined, as in the layout of the RAM. These relationships account for variable sizing of circuit features and pitch matching of circuit features. A connectivity model and a simulation model of the RAM are also produced by the method and apparatus. These model can be used to verify that the RAM is connected as desired and has the desired performance.
摘要翻译： 一种从虚拟电路描述和处理技术的规范确定随机存取存储器（RAM）的集成电路布局的方法和装置。 从电路的高级描述开始，基于相对于衬底表面的参考点开发电路的虚拟几何描述。 当指定处理技术时，确定参考点之间的关系，如RAM的布局。 这些关系涉及电路特征的可变尺寸和电路特征的音调匹配。 RAM的连接模型和仿真模型也由该方法和装置产生。 这些模型可用于验证RAM是否按需要连接并具有所需的性能。
-
17.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
-
公开(公告)号：US20140095831A1
公开(公告)日：2014-04-03
申请号：US13631071
申请日：2012-09-28
申请人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
发明人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/355
摘要： An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.
摘要翻译： 描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。 例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址 聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。
-
19.发明申请Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
-
20.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07987346B2
公开(公告)日：2011-07-26
申请号：US13011711
申请日：2011-01-21
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.019 秒)
