公开(公告)号：US10860404B2

公开(公告)日：2020-12-08

申请号：US16260965

申请日：2019-01-29

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Yi-Hua Wu ,  I-Hsin Chen ,  Chung-Hsien Liu

IPC: G06F11/07

Abstract: This application provides a server and a debugging method therefor. The debugging method for a server includes receiving, by a complex programmable logic device (CPLD), a control signal generated by a switching member, and generating a switching signal; and switching, by a bus switch, a communication connection of a communications port to a debug port or a Serial Over LAN port of a baseboard management controller (BMC) based on the switching signal. In this way, debugging work is completed or industrial control application information is received at the communications port.

公开(公告)号：US10802918B2

公开(公告)日：2020-10-13

申请号：US16244639

申请日：2019-01-10

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Lung Shen ,  Chen-Nan Hsiao ,  Chih-Cheng Wang ,  Chung-Huang Liu

IPC: G06F3/06 ,  G06F11/14

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

公开(公告)号：US10713193B2

公开(公告)日：2020-07-14

申请号：US16188458

申请日：2018-11-13

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Ming-Shou Shen

IPC: G06F3/00 ,  G06F13/20 ,  G06F11/14 ,  G06F13/12

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.

公开(公告)号：US20200159541A1

公开(公告)日：2020-05-21

申请号：US16588174

申请日：2019-09-30

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Jyun-Hong LI ,  Chi-Hao KUAN

IPC: G06F9/4401 ,  G06K9/62 ,  G06K9/46 ,  G06N20/00

Abstract: A method for identifying a boot stage of a BIOS of a computer device is provided. A control terminal receives screen information data indicative of a current BIOS screen image of the computer device, acquires current screen information based on the screen information data, acquires feature vector based on the current screen information, uses an image classification model to classify the current information into a screen category, and generates boot stage information indicative of a boot stage corresponding to the screen category.

公开(公告)号：US20200097299A1

公开(公告)日：2020-03-26

申请号：US16573864

申请日：2019-09-17

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen HUANG ,  Chen-Nan HSIAO ,  Xu ZHANG ,  Wei-Lung SHEN

IPC: G06F9/4401 ,  G06F9/445

Abstract: A synchronization method, which is capable of data synchronization in both directions between a storage medium and a storage unit, includes steps of: determining whether first parameter data of the storage medium is identical to default parameter data stored in the storage medium; determining whether a value of a flag stored in the storage unit is equal to a first logical value; and performing data synchronization between the storage unit and the storage medium based on at least one of the two determinations.

公开(公告)号：US20200097057A1

公开(公告)日：2020-03-26

申请号：US16526405

申请日：2019-07-30

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chia-Hung TSENG ,  Han-Ching HSIEH ,  Kuan-Ho LIN ,  Shun-Chi LEE

IPC: G06F1/26 ,  H05K7/14

Abstract: A server rack includes a plurality of servers, each of which includes: a power management unit operable to convert a DC input voltage into at least one DC output voltage to output at least one type of DC output power; at least one application circuit for being respectively powered by the at least one type of DC output power; and a baseboard management controller cooperating with the power management unit to provide power management data. One of the baseboard management controllers of the servers is for receiving the power management data respectively from the other one(s) of the baseboard management controllers, and controls the power management units of the servers for power management of the servers based on the power management data.

公开(公告)号：US20190286527A1

公开(公告)日：2019-09-19

申请号：US16244639

申请日：2019-01-10

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Lung SHEN ,  Chen-Nan HSIAO ,  Chih-Cheng WANG ,  Chung-Huang LIU

IPC: G06F11/14 ,  G06F3/06

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

公开(公告)号：US10223229B2

公开(公告)日：2019-03-05

申请号：US15276184

申请日：2016-09-26

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wei Wang

IPC: H04L12/24 ,  G06F11/30 ,  G06F1/20 ,  G06F13/364 ,  G06F13/40

Abstract: A system includes a bus, multiple BMCs, and a control unit. Each BMC generates heartbeat signals and acquire operation data associated with a to-be-monitored unit once being initiated, and operates in one of a master mode and a slave mode according to a corresponding decision signal. One of the BMCs which operates in the master mode is configured to receive via the bus the operation data from the rest of the BMCs which operate(s) in the slave mode for monitoring the to-be-monitored unit. The control unit is configured to, according to the heartbeat signals, generate the corresponding decision signals for controlling a first normally operating one of the BMCs to operate in the master mode and the rest of the BMCs to operate in the slave mode.

公开(公告)号：US20180285297A1

公开(公告)日：2018-10-04

申请号：US15474516

申请日：2017-03-30

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Kuo-Hua CHAN

IPC: G06F13/364 ,  H03K3/3562 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F13/4022 ,  G06F13/4282

Abstract: An HDMI apparatus and a method for controlling the same are provided. The HDMI apparatus includes an HDMI connection port, a control circuit, a master circuit, a slave circuit, and a switch circuit. The master circuit and the slave circuit are respectively configured to generate a master HDMI output signal and a slave HDMI output signal. The switch circuit is selectively conducted in a first conductive state and a second conductive state according to a control signal generated by the control circuit. In the first conductive state, the switch circuit is electrically connected to the master circuit, so that the master HDMI output signal is output through the HDMI connection port. In the second conductive state, the switch circuit is electrically connected to the slave circuit, so that the slave HDMI output signal is output through the HDMI connection port.

公开(公告)号：US10055366B2

公开(公告)日：2018-08-21

申请号：US15446558

申请日：2017-03-01

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chi-Jung Lin ,  Chi-Hao Kuan ,  Hsiang-Jui Huang

IPC: G06F13/16 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F9/4411 ,  G06F13/20 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.