公开(公告)号：US20140321185A1

公开(公告)日：2014-10-30

申请号：US13873998

申请日：2013-04-30

申请人： Perry H. Pelley ,  Peter J. Wilson

发明人： Perry H. Pelley ,  Peter J. Wilson

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C7/1075 ,  G11C8/16

摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.

摘要翻译： 存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口， 第三个港口和第四个港口。 第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。 第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。 第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。 中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

公开(公告)号：US08861289B2

公开(公告)日：2014-10-14

申请号：US13740868

申请日：2013-01-14

申请人： Perry H. Pelley

发明人： Perry H. Pelley

IPC分类号： G11C7/00 ,  G11C8/16 ,  G11C7/10

CPC分类号： G11C8/16 ,  G11C7/00 ,  G11C7/10 ,  G11C11/412 ,  G11C11/413

摘要： In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.

摘要翻译： 在多端口SRAM中，第一位单元耦合到第一和第二字线以及第一和第二位线对。 第二位单元耦合到第一和第二字线以及第三和第四位线对。 第一数据线对经由第一开关逻辑经由第一开关逻辑耦合到第一位线对，并经由第二开关逻辑耦合到第三位线对，并且第二数据线对经由第三开关逻辑耦合到第二位线对，并且耦合到第 第四位线对经由第四切换逻辑。 如果在第一和第二访问地址的至少部分之间存在匹配，则设置第三和第四切换逻辑的状态使得第二位线对和第四位线对保持与第二数据线对解耦。

公开(公告)号：US08861243B1

公开(公告)日：2014-10-14

申请号：US13873998

申请日：2013-04-30

申请人： Perry H. Pelley ,  Peter J. Wilson

发明人： Perry H. Pelley ,  Peter J. Wilson

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C7/1075 ,  G11C8/16

摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.

摘要翻译： 存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口， 第三个港口和第四个港口。 第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。 第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。 第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。 中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

公开(公告)号：US20140241100A1

公开(公告)日：2014-08-28

申请号：US13780101

申请日：2013-02-28

申请人： PERRY H. PELLEY

发明人： PERRY H. PELLEY

IPC分类号： G11C8/16

CPC分类号： G11C8/16

摘要： A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the first input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the first clock and to launch an access for the valid address provided by the second input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the second clock.

摘要翻译： 存储器系统包括具有第一端口和第二端口的多端口存储器。 第一寄存器和第二寄存器分别向第一和第二端口提供第一和第二地址。 访问控制器控制多端口存储器以响应于主时钟的第一沿来启动由第一输入寄存器提供的有效地址的访问，除非主时钟的紧前面的第一沿最近比最多发生 最近出现第一时钟的第一边缘，并且响应于主时钟的第一个边缘而启动对由第二输入寄存器提供的有效地址的访问，除非主时钟的紧接在前的第一沿比最近发生 最近出现的第二个时钟的第一个边缘。

公开(公告)号：US08796822B2

公开(公告)日：2014-08-05

申请号：US13268681

申请日：2011-10-07

申请人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

发明人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

IPC分类号： H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L22/32 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06596

摘要： A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

摘要翻译： 叠层半导体器件包括第一和第二半导体器件。 第一和第二装置中的每一个的第一主表面包括有源电路直接面对彼此。 每个装置的第一主表面包括在至少一个边缘上的斜边缘和延伸到斜边上的探针垫。 第一开口位于堆叠半导体器件的垂直侧上的第一和第二器件的斜边之间。

公开(公告)号：US08294483B2

公开(公告)日：2012-10-23

申请号：US12130173

申请日：2008-05-30

申请人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

发明人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3025

摘要： A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

摘要翻译： 测试系统包括测试仪探头和多个集成电路。 使用无载波超宽带（UWB）射频（RF）将测试广播到多个集成电路。 所有多个集成电路同时接收通过无载波UWB RF测试输入信号，并且所有多个集成电路都运行测试并基于测试输入信号提供结果。 因此，同时测试多个集成电路，这大大减少了测试时间。 此外，与集成电路的物理接触也不会妨碍测试。

公开(公告)号：US08004080B2

公开(公告)日：2011-08-23

申请号：US12554124

申请日：2009-09-04

申请人： Michael B. McShane ,  Perry H. Pelley

发明人： Michael B. McShane ,  Perry H. Pelley

IPC分类号： H01L23/34 ,  H01L29/22

CPC分类号： H01L23/13 ,  H01L23/538 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00

摘要： A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circuits having ports on the second edge. The second edges are connected to the substrate. The first major surface of the second integrated circuit is parallel with the second major surface of the first integrated circuit. The heat sink has a backplane adjacent to the third edge, a first portion along the first major surface of the first integrated circuit, a second portion along the second major surface of the second integrated circuit extending from the backplane, and an insert between the first major surface of the second integrated circuit and the second major surface of the first integrated circuit.

摘要翻译： 模块具有基板，第一和第二集成电路以及散热器。 集成电路各自具有第一主表面，第二主表面，第一边缘，第二边缘和第三边缘，并且具有在第一边缘上具有端口的光电路，并且具有在第二边缘上的端口的电子电路。 第二边缘连接到基板。 第二集成电路的第一主表面与第一集成电路的第二主表面平行。 散热器具有与第三边缘相邻的背板，沿着第一集成电路的第一主表面的第一部分，沿着从背板延伸的第二集成电路的第二主表面的第二部分，以及在第一 第二集成电路的主表面和第一集成电路的第二主表面。

公开(公告)号：US20110115554A1

公开(公告)日：2011-05-19

申请号：US12621005

申请日：2009-11-18

申请人： Perry H. PELLEY

发明人： Perry H. PELLEY

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/009

摘要： A system includes a first circuit, a first charge pump, a second circuit, and a second charge pump. The first circuit has a first power supply terminal coupled to a positive power supply terminal and a second power supply terminal. The first charge pump has an input coupled to positive power supply terminal and an output coupled to the second power supply terminal of the first circuit. The second circuit has a first power supply terminal coupled the second power supply terminal of the first circuit and a second power supply terminal. The second charge pump has an input coupled to the first power supply terminal of the second circuit and an output coupled to the second power supply terminal of the second circuit.

摘要翻译： 系统包括第一电路，第一电荷泵，第二电路和第二电荷泵。 第一电路具有耦合到正电源端子和第二电源端子的第一电源端子。 第一电荷泵具有耦合到正电源端子的输入端和耦合到第一电路的第二电源端子的输出端。 第二电路具有耦合第一电路的第二电源端和第二电源端的第一电源端。 第二电荷泵具有耦合到第二电路的第一电源端子的输入端和耦合到第二电路的第二电源端子的输出端。

公开(公告)号：US20110093660A1

公开(公告)日：2011-04-21

申请号：US12972878

申请日：2010-12-20

申请人： PERRY H. PELLEY, III ,  GEORGE P. HOEKSTRA ,  LUCIO F.C. PESSOA

发明人： PERRY H. PELLEY, III ,  GEORGE P. HOEKSTRA ,  LUCIO F.C. PESSOA

IPC分类号： G06F12/08

CPC分类号： G06F15/16

摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

摘要翻译： 系统在第一相干组中具有第一多个核心。 每个核心以数据包传输数据。 核心直接串联耦合以形成串行路径。 数据包沿串行路径传输。 串行路径在一端耦合到分组交换机。 分组交换机耦合到存储器。 第一多个核心和分组交换机在集成电路上。 存储器可能集成在或不在集成电路上。 在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。 可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

公开(公告)号：US07791367B1

公开(公告)日：2010-09-07

申请号：US12479093

申请日：2009-06-05

申请人： Perry H. Pelley

发明人： Perry H. Pelley

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/018585

摘要： An integrated circuit is configured to be in a calibration mode of operation to establish a desired output impedance of a driver circuit. A predetermined constant voltage is established at a circuit node within the integrated circuit. A calibration current is conducted through a transistor connected in series with a variable value resistance in the integrated circuit at the circuit node. A resistance value of the variable value resistance is varied to establish a value of the calibration current which establishes the desired output impedance. The calibration mode is exited and a functional mode is entered. A calibrated resistance value is used during the functional mode of operation. The calibration current is conducted as a calibrated current through the transistor and calibrated resistance value. Variation of the calibrated current is corrected in response to voltage and process variations to maintain the calibrated current and output impedance of the driver circuit.

摘要翻译： 集成电路被配置为处于校准操作模式以建立驱动器电路的期望的输出阻抗。 在集成电路内的电路节点处建立预定的恒定电压。 校准电流通过在电路节点处的集成电路中与可变电阻电阻串联连接的晶体管进行。 改变可变电阻电阻的电阻值以建立建立期望的输出阻抗的校准电流的值。 退出校准模式，并输入功能模式。 在功能运行模式下使用校准电阻值。 校准电流通过晶体管和校准电阻值作为校准电流进行。 校准电流的变化是响应于电压和过程变化而被校正的，以维持驱动器电路的校准电流和输出阻抗。