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公开(公告)号：US09672938B2
公开(公告)日：2017-06-06
申请号：US14258730
申请日：2014-04-22
摘要： Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.
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公开(公告)号：US20160035415A1
公开(公告)日：2016-02-04
申请号：US14448174
申请日：2014-07-31
CPC分类号： G11C13/004 , G11C8/14 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C2013/0071 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.
摘要翻译： 存储单元包括具有直接连接到第一电源轨的第一端子和耦合到内部节点的第二端子的单个双向电阻存储元件（BRME）; 以及第一晶体管，其具有耦合到所述内部节点的控制电极，以及耦合到第一位线的第一电流电极和耦合到由读取字线和所述第一电力轨道组成的组中的一个的第二电流电极。
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公开(公告)号：US09236795B2
公开(公告)日：2016-01-12
申请号：US14182702
申请日：2014-02-18
申请人： Perry H. Pelley , Michael G. Neaves
发明人： Perry H. Pelley , Michael G. Neaves
CPC分类号： H02M3/07 , H02M2001/0003
摘要： A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.
摘要翻译： 电荷泵系统包括具有耦合到第一参考电压的第一输入的比较器，耦合到反馈信号的第二输入和耦合到控制压控振荡器的操作的输出。 反馈信号耦合到电荷泵系统的输出端。 放大器具有耦合到第二参考电压的第一输入，耦合到反馈信号的第二输入和耦合到压控振荡器的输入的输出。 放大器的增益低于比较器的增益。
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公开(公告)号：US20150244375A1
公开(公告)日：2015-08-27
申请号：US14191684
申请日：2014-02-27
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译： 一种用于确定相对于阈值温度的温度阈值指示的电路。 电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。 在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。 响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。
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公开(公告)号：US20150236584A1
公开(公告)日：2015-08-20
申请号：US14182702
申请日：2014-02-18
申请人： Perry H. Pelley , Michael G. Neaves
发明人： Perry H. Pelley , Michael G. Neaves
IPC分类号： H02M3/07
CPC分类号： H02M3/07 , H02M2001/0003
摘要： A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.
摘要翻译： 电荷泵系统包括具有耦合到第一参考电压的第一输入的比较器，耦合到反馈信号的第二输入和耦合到控制压控振荡器的操作的输出。 反馈信号耦合到电荷泵系统的输出端。 放大器具有耦合到第二参考电压的第一输入，耦合到反馈信号的第二输入和耦合到压控振荡器的输入的输出。 放大器的增益低于比较器的增益。
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公开(公告)号：US09111634B2
公开(公告)日：2015-08-18
申请号：US13548843
申请日：2012-07-13
申请人： Perry H. Pelley , James D. Burnett
发明人： Perry H. Pelley , James D. Burnett
IPC分类号： H01L23/522 , G11C11/412 , G11C7/18 , G11C7/02 , G11C5/06 , G11C8/16 , H01L21/8228
CPC分类号： H01L27/11 , G11C5/063 , G11C7/02 , G11C7/18 , G11C8/16 , G11C11/412 , H01L21/768 , H01L21/8228 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.
摘要翻译： 存储器件包括使用衬底形成的存储单元，用于承载数据位的真位线BL0以及用于承载第一真位位线所携带的数据位的互补位线的互补位线。 真正的位线耦合到存储单元并横向延伸到衬底上。 真位线和互补位线彼此相邻并且垂直地堆叠在衬底上。
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7.发明授权公开(公告)号：US09099475B2
公开(公告)日：2015-08-04
申请号：US13611076
申请日：2012-09-12
IPC分类号： H05K1/00 , H05K7/00 , G02B6/12 , H01L23/02 , H01L23/48 , G11C5/06 , H01L23/538 , H01L25/04 , H01L25/065 , H01L23/00
CPC分类号： H01L23/48 , H01L23/538 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L25/04 , H01L25/0657 , H01L2224/131 , H01L2224/16146 , H01L2224/24146 , H01L2224/245 , H01L2224/2518 , H01L2224/32135 , H01L2224/73217 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/83 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2224/97 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/01029 , H01L2924/01013 , H01L2224/81 , H01L2924/014
摘要： An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.
摘要翻译： 电子组件包括处理器模具组件，第一模具组件和第二模具组件。 第一模具组件定位在处理器模具组件的第一侧上。 第二模具组件位于处理器模具组件的与处理器模具组件的第一侧相对的第二侧。 通孔将第一和第二模具组件耦合到处理器模具组件。
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公开(公告)号：US20150115474A1
公开(公告)日：2015-04-30
申请号：US14068637
申请日：2013-10-31
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/02 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L29/0657 , H01L2224/04 , H01L2224/04042 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/80001 , H01L2224/92165 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/10156 , H01L2924/10158 , H01L2924/12042 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.
摘要翻译： 提供第一半导体器件裸片，其具有结合有切口结构的底部边缘，该切口结构允许足够的高度和宽度间隙用于连接到第一半导体器件裸片的第二半导体器件裸片的有源表面上的接合焊盘的引线接合 。 使用这种切口结构降低了结合第一和第二半导体器件管芯的堆叠的高度，从而也减小了结合堆叠的半导体器件封装的厚度。
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公开(公告)号：US20150115463A1
公开(公告)日：2015-04-30
申请号：US14069186
申请日：2013-10-31
CPC分类号： H01L23/481 , H01L21/4857 , H01L21/486 , H01L21/76898 , H01L22/32 , H01L23/36 , H01L23/42 , H01L23/5256 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/24146 , H01L2224/291 , H01L2224/29188 , H01L2224/2919 , H01L2224/29191 , H01L2224/2929 , H01L2224/29393 , H01L2224/32145 , H01L2224/33181 , H01L2224/33183 , H01L2224/821 , H01L2224/83805 , H01L2224/8385 , H01L2224/83851 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06589 , H01L2924/12042 , H01L2924/1434 , H01L2224/03 , H01L2224/83 , H01L2924/014 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.
摘要翻译： 叠层半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的第一和第二半导体器件，第一和第二半导体器件的第一主表面包括有源电路。 第一和第二半导体器件被堆叠，使得第一半导体器件的第一主表面面向第二半导体器件的第一主表面。 至少一个连续导电通孔从第一半导体器件的第二主表面延伸到第二半导体器件的第一主表面。 导电材料填充与接触垫相邻的空腔并与接触垫的一侧接触。 第一半导体器件的接触焊盘的另一侧面向并与第二半导体器件的接触焊盘的另一侧接触。
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公开(公告)号：US08917136B1
公开(公告)日：2014-12-23
申请号：US14151886
申请日：2014-01-10
摘要： A charge pump system includes a charge pump, a switchable impedance, a comparator, and a capacitor. The switchable impedance has an input coupled to the output of the charge pump. The comparator has a first input coupled to the output of the switchable impedance, a second input coupled to a reference, and an output coupled to the input of the charge pump. The capacitor has a first terminal coupled to the output of the charge pump and a second terminal coupled to the first input of the comparator. The switchable impedance causes a first impedance between the first and second terminals of the capacitor during a start-up operation of the charge pump system and a second impedance between the first and second terminals of the capacitor during a steady-state operation of the charge pump system, wherein the first impedance is lower than the second impedance.
摘要翻译： 电荷泵系统包括电荷泵，可切换阻抗，比较器和电容器。 可切换阻抗具有耦合到电荷泵的输出的输入。 比较器具有耦合到可切换阻抗的输出的第一输入，耦合到基准的第二输入和耦合到电荷泵的输入的输出。 电容器具有耦合到电荷泵的输出的第一端子和耦合到比较器的第一输入端的第二端子。 可切换阻抗在电荷泵系统的启动操作期间引起电容器的第一和第二端子之间的第一阻抗，以及在电荷泵的稳态操作期间电容器的第一和第二端子之间的第二阻抗 系统，其中第一阻抗低于第二阻抗。
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