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公开(公告)号：US4129863A
公开(公告)日：1978-12-12
申请号：US838908
申请日：1977-10-03
申请人： Paul R. Gray , James L. McCreary , David A. Hodges
发明人： Paul R. Gray , James L. McCreary , David A. Hodges
摘要： An array of binary weighed capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.
摘要翻译： 二进制加权电容器阵列，具有与二进制加权电容器中最少的电容值相当的电容值的附加电容器，电压比较器，用于将电容器与某些预定电压电平互连的开关和比较器，以及排序电路 。 所有电容器的一侧连接到比较器上的一个输入端子，而另一侧则向其施加要量化的信号。 开关顺序将参考电压的分割部分与要量化的信号相结合，以便呈现给比较器的输入，从而提供连接到排序电路的串行数字输出。 以这种方式，由定序电路进行模拟和数字信号之间的线性转换。 还公开了数字和模拟信号呈现之间的非线性转换器。
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公开(公告)号：US6079649A
公开(公告)日：2000-06-27
申请号：US185268
申请日：1998-11-03
申请人： Loran R. Balvanz , Paul R. Gray
发明人： Loran R. Balvanz , Paul R. Gray
CPC分类号： B02C13/13 , B02C13/09 , B02C13/2804
摘要： A rotor assembly for use with size reducing machines having a drive motor comprising a central shaft with a drive end for securement to the drive motor and an opposing outboard end. The rotor assembly also comprises a webbing engaged with the central shaft for supporting the rotor assembly, a rotor casing substantially seals the webbing, and a plurality of sockets secure to a plurality of casing throughbores. The webbing comprises a drive end plate secured to the central shaft with a bushing, an outboard end plate secured to the central shaft with a bushing, and a plurality of web socket supports aligned in two transversely aligned rows. The web socket plates each comprise two socket receiver channels for alignment with the sockets. Finally, a plurality of hammers releasably secure to the plurality of sockets.
摘要翻译： 一种用于具有减速机的转子组件，其具有驱动马达，所述驱动马达包括具有用于固定到驱动马达的驱动端和相对的外侧端的中心轴。 转子组件还包括与中心轴接合以用于支撑转子组件的织带，转子壳体基本上密封织带，以及固定到多个套管通孔的多个插座。 所述织带包括用衬套固定到所述中心轴的驱动端板，用衬套固定到所述中心轴的外侧端板，以及以两个横向排列的排列对准的多个腹板座。 腹板插座板各自包括用于与插座对准的两个插座接收器通道。 最后，多个锤可释放地固定到多个插座。
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公开(公告)号：US5559470A
公开(公告)日：1996-09-24
申请号：US391256
申请日：1995-02-17
申请人： Carlos A. Laber , Paul R. Gray
发明人： Carlos A. Laber , Paul R. Gray
CPC分类号： H03H11/0466
摘要： A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.
摘要翻译： 描述了使用有源积分器的快速寄生不敏感连续时间滤波器和均衡器集成电路。 还描述了用于超相消除的电路技术以及用于设置滤波器和均衡器的转角频率。 这些技术导致滤波器和均衡器芯片，其性能与过程，电源和温度无关，而不使用锁相环。 这种20MHz的第6级贝塞尔滤波器和二阶均衡器在5V工作，在处理2Vp-p差分输出信号时，仅产生总谐波失真的0.24％（-52dB）。 该器件经过优化，以限制高频噪声和幅度均衡硬盘读通道系统中的数据脉冲。 该器件支持高达36Mbps的数据速率，内置1.5Mb / 4GHz BiCMOS技术。
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14.发明授权
公开(公告)号：US5508570A
公开(公告)日：1996-04-16
申请号：US9820
申请日：1993-01-27
申请人： Carlos A. Laber , Paul R. Gray
发明人： Carlos A. Laber , Paul R. Gray
CPC分类号： G06G7/186 , G11B20/10009 , H03H11/04
摘要： A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit uses an active integrator. The integrator has a left-half plane pole. A feedback path is provided that includes a resistive impedance which comprises a MOS transistor operated in the triode region. The resistive impedance is adjustable for cancelling the pole. The feedback path also includes a capacitive impedance coupled in series with the resistive impedance.
摘要翻译： 快速寄生不敏感连续时间滤波器和均衡器集成电路使用有源积分器。 积分器具有左半平面极。 提供反馈路径，其包括电阻性阻抗，其包括在三极管区域中操作的MOS晶体管。 电阻阻抗可以调整以取消极点。 反馈路径还包括与电阻阻抗串联耦合的电容性阻抗。
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公开(公告)号：US4742330A
公开(公告)日：1988-05-03
申请号：US45349
申请日：1987-05-01
申请人： Joey Doernberg , Paul R. Gray , David A. Hodges
发明人： Joey Doernberg , Paul R. Gray , David A. Hodges
摘要： A flash ADC utilizes parallel weighted capacitive arrays and a resistor string to provide reference voltage intervals and an encoder for indicating the reference voltage interval wherein an input voltage lies. For an embodiment having N branches, the reference voltage intervals are subdivided into N sub-intervals and each succeeding clock cycle.
摘要翻译： 闪存ADC使用并行加权电容阵列和电阻串来提供参考电压间隔，以及用于指示输入电压所在的参考电压间隔的编码器。 对于具有N个分支的实施例，参考电压间隔被细分为N个子间隔和每个后续时钟周期。
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公开(公告)号：US4050031A
公开(公告)日：1977-09-20
申请号：US662462
申请日：1976-03-01
申请人： Paul R. Gray , Mark L. Stephens
发明人： Paul R. Gray , Mark L. Stephens
摘要： An amplifier circuit and structure having high input impedance and having a return path for conducting amplifier DC leakage current. A common diode structure forms the return path and includes two diodes connected in series and connected in opposite conduction directions. The diode having a forward conduction direction which is in the opposite direction of the leakage current is provided with a reverse saturation current which is substantially greater than the leakage current of the amplifier. The amplifier is typically a P channel or N channel field effect transistor (FET) and the double diode structure is typically an NPN or PNP transistor.
摘要翻译： 具有高输入阻抗并具有用于传导放大器DC漏电流的返回路径的放大器电路和结构。 公共二极管结构形成返回路径并且包括串联连接并且以相反的导通方向连接的两个二极管。 具有与漏电流相反方向的正向导通方向的二极管设置有大于放大器的漏电流的反向饱和电流。 放大器通常是P沟道或N沟道场效应晶体管（FET），双二极管结构通常是NPN或PNP晶体管。
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公开(公告)号：US4897611A
公开(公告)日：1990-01-30
申请号：US264401
申请日：1988-10-28
申请人： Carlos A. Laber , Paul R. Gray
发明人： Carlos A. Laber , Paul R. Gray
CPC分类号： H03F3/45192 , H03F1/38 , H03F3/3001
摘要： This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.
摘要翻译： 本发明用于跨导放大器。 放大器具有放大器输入和具有放大器输出阻抗的放大器输出。 放大器的输入级具有第一跨导。 中间状态通过正反馈耦合到放大器输出端。 中间级具有第二跨导和具有中间输出阻抗的中间级输出。 放大器的增益是第一跨导乘以放大器输出阻抗乘以中间输出阻抗的第二跨导的函数。
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公开(公告)号：US4166269A
公开(公告)日：1979-08-28
申请号：US883486
申请日：1978-03-06
申请人： Mark L. Stephens , Paul R. Gray
发明人： Mark L. Stephens , Paul R. Gray
摘要： A temperature compensated piezoresistive transducer includes a silicon body having a major top surface and an under surface. The body has generally parallel spaced first and second elongate slots formed therein extending through said top and under surfaces to define a center portion between said slots and first and second outer portions at the outward edge of the respective slots. The center portion is adapted to receive pressure to be measured. The body has an additional slot extending through the top and bottom surfaces and extending around the first, second and center portions to define the outer periphery of a transducer membrane with portions of the body remaining to integrally support the membrane. Plural piezoresistive elements having elongate and transverse dimensions are formed on the membrane. The elements are arrayed to receive compressive and tensile stress when pressure is applied.
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