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    Latch structure for interlocked pipelined CMOS (IPCMOS) circuits
    12.
    发明授权
    Latch structure for interlocked pipelined CMOS (IPCMOS) circuits 失效
    用于联锁流水线CMOS（IPCMOS）电路的锁存结构

    公开(公告)号：US06829716B2

    公开(公告)日：2004-12-07

    申请号：US09836375

    申请日：2001-04-17

    Applicant: Peter W. Cook ,  Stanley E. Schuster

    Inventor： Peter W. Cook ,  Stanley E. Schuster

    IPC: G06F104

    CPC classification number: G06F7/00 ,  G06F9/3869 ,  G06F9/3871

    Abstract: Circuits and methods for operating a latch structure are disclosed. The circuits include a plurality of stages, and each stage includes a first logic circuit, a latch coupled to a second logic circuit of an adjacent stage and a switch which connects the first logic circuit to the latch in a first state and disconnects the logic circuit from the latch in a second state. A local clock circuit controls the first and second states by providing a locally generated clock signal to activate the switch. The locally generated clock signals are generated by interlocking handshake signals from a local clock circuit of an adjacent stage.

    Abstract translation: 公开了用于操作闩锁结构的电路和方法。 电路包括多个级，并且每个级包括第一逻辑电路，耦合到相邻级的第二逻辑电路的锁存器和在第一状态下将第一逻辑电路连接到锁存器的开关，并且断开逻辑电路 从第二状态的锁存器。 本地时钟电路通过提供本地生成的时钟信号来激活开关来控制第一和第二状态。 本地生成的时钟信号通过来自相邻级的本地时钟电路的互锁信号产生。

    Radiant energy control system
    13.
    发明授权
    Radiant energy control system 失效
    辐射能量控制系统

    公开(公告)号：US06505099B1

    公开(公告)日：2003-01-07

    申请号：US09172783

    申请日：1998-10-14

    Applicant: Martin S. Brice ,  Gordon M. Kay ,  Peter W. Cook

    Inventor： Martin S. Brice ,  Gordon M. Kay ,  Peter W. Cook

    IPC: G01M138

    CPC classification number: F24D19/10 ,  F24D5/08 ,  G05D23/19

    Abstract: In a radiant energy heating system having one or more types of radiant energy heating sub-systems, a control system comprising a solid state electronic control panel pre-programmed to control two or more of the types of radiant heating sub-systems, wherein the control panel controls one or more of the types of sub-systems.

    Abstract translation: 在具有一种或多种类型的辐射能量加热子系统的辐射能量加热系统中，控制系统包括预编程以控制两种或多种辐射加热子系统的固态电子控制面板，其中控制 面板控制一个或多个类型的子系统。

    IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
    14.
    发明授权
    IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle 失效
    IC芯片包括ALU和相同的寄存器文件，由此多个ALU直接并且同时向每个周期的每个寄存器文件写入结果

    公开(公告)号：US5301340A

    公开(公告)日：1994-04-05

    申请号：US607176

    申请日：1990-10-31

    Applicant: Peter W. Cook

    Inventor： Peter W. Cook

    IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F15/80 ,  G06F15/76

    CPC classification number: G06F9/3891 ,  G06F15/8015 ,  G06F9/3012 ,  G06F9/3885 ,  G06F9/3887

    Abstract: A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.

    Abstract translation: 并行计算机体系结构包含用于并行ALU的新的寄存器文件组织，由于减少的片外交叉和局部更高的密度，提供了改进的性能。 每个ALU都配有自己的较小的寄存器文件，位于ALU芯片上。 由一个ALU写入的数据被“广播”到所有的“本地”寄存器文件。 这种“本地”寄存器文件的布置使所需的引脚数量最小化，并且使用非常大规模的集成（VLSI）技术可以实现高密度。 这些“本地”寄存器文件消除了片外延迟，并且通过本地寄存器文件中较短的线长进一步增强了性能。

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