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    Latch structure for interlocked pipelined CMOS (IPCMOS) circuits
    2.
    发明授权
    Latch structure for interlocked pipelined CMOS (IPCMOS) circuits 失效
    用于联锁流水线CMOS（IPCMOS）电路的锁存结构

    公开(公告)号：US06829716B2

    公开(公告)日：2004-12-07

    申请号：US09836375

    申请日：2001-04-17

    Applicant: Peter W. Cook ,  Stanley E. Schuster

    Inventor： Peter W. Cook ,  Stanley E. Schuster

    IPC: G06F104

    CPC classification number: G06F7/00 ,  G06F9/3869 ,  G06F9/3871

    Abstract: Circuits and methods for operating a latch structure are disclosed. The circuits include a plurality of stages, and each stage includes a first logic circuit, a latch coupled to a second logic circuit of an adjacent stage and a switch which connects the first logic circuit to the latch in a first state and disconnects the logic circuit from the latch in a second state. A local clock circuit controls the first and second states by providing a locally generated clock signal to activate the switch. The locally generated clock signals are generated by interlocking handshake signals from a local clock circuit of an adjacent stage.

    Abstract translation: 公开了用于操作闩锁结构的电路和方法。 电路包括多个级，并且每个级包括第一逻辑电路，耦合到相邻级的第二逻辑电路的锁存器和在第一状态下将第一逻辑电路连接到锁存器的开关，并且断开逻辑电路 从第二状态的锁存器。 本地时钟电路通过提供本地生成的时钟信号来激活开关来控制第一和第二状态。 本地生成的时钟信号通过来自相邻级的本地时钟电路的互锁信号产生。

    Radiant energy control system
    3.
    发明授权
    Radiant energy control system 失效
    辐射能量控制系统

    公开(公告)号：US06505099B1

    公开(公告)日：2003-01-07

    申请号：US09172783

    申请日：1998-10-14

    Applicant: Martin S. Brice ,  Gordon M. Kay ,  Peter W. Cook

    Inventor： Martin S. Brice ,  Gordon M. Kay ,  Peter W. Cook

    IPC: G01M138

    CPC classification number: F24D19/10 ,  F24D5/08 ,  G05D23/19

    Abstract: In a radiant energy heating system having one or more types of radiant energy heating sub-systems, a control system comprising a solid state electronic control panel pre-programmed to control two or more of the types of radiant heating sub-systems, wherein the control panel controls one or more of the types of sub-systems.

    Abstract translation: 在具有一种或多种类型的辐射能量加热子系统的辐射能量加热系统中，控制系统包括预编程以控制两种或多种辐射加热子系统的固态电子控制面板，其中控制 面板控制一个或多个类型的子系统。

    IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
    4.
    发明授权
    IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle 失效
    IC芯片包括ALU和相同的寄存器文件，由此多个ALU直接并且同时向每个周期的每个寄存器文件写入结果

    公开(公告)号：US5301340A

    公开(公告)日：1994-04-05

    申请号：US607176

    申请日：1990-10-31

    Applicant: Peter W. Cook

    Inventor： Peter W. Cook

    IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F15/80 ,  G06F15/76

    CPC classification number: G06F9/3891 ,  G06F15/8015 ,  G06F9/3012 ,  G06F9/3885 ,  G06F9/3887

    Abstract: A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.

    Abstract translation: 并行计算机体系结构包含用于并行ALU的新的寄存器文件组织，由于减少的片外交叉和局部更高的密度，提供了改进的性能。 每个ALU都配有自己的较小的寄存器文件，位于ALU芯片上。 由一个ALU写入的数据被“广播”到所有的“本地”寄存器文件。 这种“本地”寄存器文件的布置使所需的引脚数量最小化，并且使用非常大规模的集成（VLSI）技术可以实现高密度。 这些“本地”寄存器文件消除了片外延迟，并且通过本地寄存器文件中较短的线长进一步增强了性能。

    Partial decode shifter/rotator
    7.
    发明授权
    Partial decode shifter/rotator 失效
    部分解码移位器/旋转器

    公开(公告)号：US4931971A

    公开(公告)日：1990-06-05

    申请号：US297170

    申请日：1989-01-13

    Applicant: Peter W. Cook ,  Robert K. Montoye

    Inventor： Peter W. Cook ,  Robert K. Montoye

    IPC: G06F5/01 ,  G06F7/00 ,  G06F7/76

    CPC classification number: G06F5/015

    Abstract: A data shifter/rotator which is comprised of two levels of s, where s is an integer >2, way switches. The outputs of the first level are connected to the corresponding inputs of the second level. There are first and second control words, with the first control word controlling the amount of the shift/rotation in the first level, and the second control word controlling the amount of the shift/rotation in the second level. The amount of the shift/rotation is determined by the position of the s way switches in each level, as selected by the respective control words.

    Avoidance of hot electron operation of voltage stressed bootstrap drivers
    8.
    发明授权
    Avoidance of hot electron operation of voltage stressed bootstrap drivers 失效
    避免电压应力引导驱动器的热电子操作

    公开(公告)号：US4199695A

    公开(公告)日：1980-04-22

    申请号：US883429

    申请日：1978-03-03

    Applicant: Peter W. Cook ,  Stanley E. Schuster

    Inventor： Peter W. Cook ,  Stanley E. Schuster

    IPC: H01L27/04 ,  G06F1/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/082 ,  H03K19/003 ,  H03K19/017 ,  H03K3/353

    CPC classification number: H03K5/023 ,  G06F1/04 ,  H01L27/06 ,  H01L29/78 ,  H03K17/0822 ,  H03K19/00315 ,  H03K19/01714

    Abstract: An improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a simultaneous gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range. The voltage control means is adapted to reduce FET drain to source voltage by connecting a plurality of FET devices in series to reduce the drain to source voltage drop across each device. The drain to source voltage is further defined by connecting the common nodes of successive series connected devices to a specified voltage source that is less than a characteristic hot electron drain to source voltage. The voltage control means also includes a gate voltage clamping FET that is adapted to hold down the gate of a device when the drain to source voltage of the device rises above a particular hot electron voltage. The voltage control means further comprises a plurality of timing pulses that define particular combinations of gate and drain to source device voltages that are less than characteristic combined hot electron voltages. The voltage control means further includes devices with width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages to maintain a minimum drain to source voltage drop. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.

    Abstract translation: 一种改进的场效应晶体管电路，适于在高开关速度下工作并避免受压应力FET自举驱动器的热电子操作。 该电路包括电压控制装置，其适于在特征热电子工作电压范围内保持FET器件的同时栅极和漏极到源极电压。 电压控制装置适于通过串联连接多个FET器件来减少FET漏极到源极电压，以减少跨越每个器件的漏极到源极电压降。 通过将连续串联连接的器件的公共节点连接到小于特征热电子漏极到源极电压的指定电压源，进一步限定漏极到源极电压。 电压控制装置还包括栅极电压钳位FET，其适于在器件的漏极 - 源极电压升高到特定热电子电压之上时压住器件的栅极。 电压控制装置还包括多个定时脉冲，其限定小于特征组合热电子电压的栅极和漏极与源极器件电压的特定组合。 电压控制装置还包括宽度与长度比适合于在输入漏极电压和输出源电压之间提供紧密电压跟踪的装置，以保持对源极电压降的最小漏极。 关于使用电压应力自举驱动器FET以产生片上时钟相位的实施例，特别描述了热电子电压控制装置的操作。

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