公开(公告)号：US07359932B2

公开(公告)日：2008-04-15

申请号：US10318516

申请日：2002-12-12

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

IPC: G06F15/76 ,  G06F15/163

CPC classification number: H04L69/16 ,  G06F15/17 ,  H04L12/42 ,  H04L67/1002 ,  H04L69/161 ,  H04W28/14

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract translation: 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。

公开(公告)号：US07308558B2

公开(公告)日：2007-12-11

申请号：US10752959

申请日：2004-01-07

Applicant: Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

IPC: G06F15/16 ,  G06F16/163

CPC classification number: G06F15/17381

Abstract: The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.

Abstract translation: 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个应用中，数据处理系统包括第一和第二处理簿，每个书籍至少包括第一和第二处理单元。 第一和第二处理单元中的每一个具有相应的第一输出数据总线。 第一处理单元的第一输出数据总线耦合到第二处理单元，第二处理单元的第一输出数据总线耦合到第一处理单元。 至少第一处理簿的第一处理单元和第二处理簿的第二处理单元各自具有相应的第二输出数据总线。 第一处理簿的第一处理单元的第二输出数据总线耦合到第二处理器书的第一处理单元，第二处理器书的第二处理单元的第二输出数据总线耦合到第二处理器 第一个处理器书的单位。

公开(公告)号：US07130967B2

公开(公告)日：2006-10-31

申请号：US10733948

申请日：2003-12-10

Applicant: Ravi Kumar Arimilli ,  Sanjeev Ghai ,  Warren Edward Maule

Inventor： Ravi Kumar Arimilli ,  Sanjeev Ghai ,  Warren Edward Maule

IPC: G06F12/00

CPC classification number: G06F9/383 ,  G06F9/3832 ,  G06F9/3851 ,  G06F12/0215

Abstract: A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.

Abstract translation: 数据处理系统包括一个或多个处理核心，具有多行数据存储的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控​​制器。 存储器控制器包括存储有关先前存储器访问的历史信息的存储器推测表。 响应于存储器访问请求，存储器控制器引导对系统存储器中的所选行的访问以服务存储器访问请求。 存储器控制器推测地指示在基于存储器推测表中的历史信息的访问之后，所选择的行将继续被通电，使得紧随其后的存储器访问的访问等待时间减少。

公开(公告)号：US07117388B2

公开(公告)日：2006-10-03

申请号：US10424278

申请日：2003-04-28

Applicant: Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

Inventor： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

IPC: G06F11/00

CPC classification number: G06F11/2043 ,  G06F11/2028 ,  G06F11/2289

Abstract: A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.

Abstract translation: 一种用于动态检测热插拔处理系统中的问题组件的方法，系统和数据处理系统，并且通过热删除方法自动移除问题组件，而不会中断整个系统的处理。 提供无中断的热插拔功能的数据处理系统设计有一个额外的逻辑，用于启动和/或完成热插拔组件上的一系列工厂级测试，以确定组件是否正常工作。 当组件运行不正常时，操作系统将组件的工作负载重新分配给其他组件，以便系统，并且当操作系统完成重新分配时，服务组件启动组件的热删除，以使组件 与系统逻辑和电气分离。

公开(公告)号：US07117319B2

公开(公告)日：2006-10-03

申请号：US10313321

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F12/00

CPC classification number: G06F9/462 ,  G01R31/318536 ,  G06F9/30101 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/3013

Abstract: A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.

Abstract translation: 公开了一种用于管理对于在处理器中执行处理至关重要的处理器的硬结构状态的方法和系统。 当处理器接收到中断时，硬设计状态的卷影副本从处理器存储到存储器。 硬架构的卷影副本允许快速保存中断过程的硬结构状态，从而可以将下一个进程的架构状态立即存储在处理器中。

公开(公告)号：US07073043B2

公开(公告)日：2006-07-04

申请号：US10425425

申请日：2003-04-28

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

IPC: G06F12/00

CPC classification number: G06F12/1072 ,  G06F12/1027 ,  G06F2212/682

Abstract: Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a “barrier” class instruction.

Abstract translation: 公开了一种实现TLBI协议的对称多处理器数据处理系统（SMP），其允许来自分区内的多个处理器的多个TLBI操作同时完成。 因此，不需要全局TLB锁定，同步和TLB解锁。 当执行TLBI指令时，主机基于异步侦听另一个TLBI动态管理TLBI操作的行为。 如果需要并发TLBI管理，则主机将TLBI动态地降级为“障碍”类指令。

公开(公告)号：US06990545B2

公开(公告)日：2006-01-24

申请号：US10424277

申请日：2003-04-28

Applicant: Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

Inventor： Ravi Kumar Arimilli ,  Michael Stephen Floyd ,  Kevin Franklin Reick

IPC: G06F13/00

CPC classification number: G06F13/4081

Abstract: A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.

Abstract translation: 一种数据处理系统，可为单个热插拔组件提供热插拔添加和删除功能，而不会中断整个处理系统的当前操作。 处理系统包括互连结构，其包括热插拔连接器，外部可热插拔组件可以连接到数据处理系统，逻辑组件包括配置逻辑和路由和操作逻辑。 当热插拔组件连接到热插拔连接器时，服务元件会自动检测连接并为扩展系统选择正确的配置文件。 一旦加载了配置文件，并且新元素的系统检查指示新元素可以进行集成，则将新元素集成到现有系统中，并且操作系统将工作负载分配给新元素。 从客户的角度来看，整个过程都是在不掉电或破坏现有元素的操作的情况下进行的。

公开(公告)号：US06986011B2

公开(公告)日：2006-01-10

申请号：US10313323

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

IPC: G06F12/00

CPC classification number: G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0831

Abstract: A processor chip with a high speed memory cloner that enables movement of data directly from one memory location (of a data processing system) to another without the data having to be routed through the processor. The memory cloner includes processing logic that enables the release of the processor to continue processing other operations while the data are physically moved in the background. The memory cloner generates a sequence of naked writes (i.e., write operations with no data tenure) from the write data commands and forwards the naked writes to the memory controller of the destination memory module. When all the naked write operations receive a Null response (i.e., a response indicating that the specific addressed at the memory module are reserved/set to receive data), the memory cloner signals the processor that the move request is completed. The memory cloner also comprises a source and a destination address buffer and a count register, within which are stored the source and destination addresses and the number of bytes of data to be moved.

Abstract translation: 具有高速存储器克隆器的处理器芯片，其能够将数据直接从数据处理系统的一个存储器位置移动到另一个，而不需要通过处理器路由数据。 存储器克隆器包括处理逻辑，其能够释放处理器以在数据在后台物理移动的同时继续处理其它操作。 存储器克隆器从写入数据命令产生一系列裸写（即，没有数据保留的写入操作），并将裸写入转发到目的地存储器模块的存储器控​​制器。 当所有的裸写操作都接收到空响应（即，指示在存储器模块处寻址的特定被保留/设置为接收数据的响应）时，存储器克隆器向处理器发信号通知移动请求完成。 存储器克隆还包括源和目的地地址缓冲器和计数寄存器，其中存储源和目的地址以及要移动的数据的字节数。

公开(公告)号：US06976148B2

公开(公告)日：2005-12-13

申请号：US10339766

申请日：2003-01-09

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081

Abstract: An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

Abstract translation: I / O通信适配器从处理器核心接收参考在处理器核心的有效地址空间内识别存储位置的有效地址的I / O命令。 响应于I / O命令的接收，I / O通信适配器通过参考翻译数据结构将有效地址转换成实地址。 然后，I / O通信适配器使用实际地址访问存储位置，以执行由I / O命令指定的I / O数据传输。

公开(公告)号：US06848003B1

公开(公告)日：2005-01-25

申请号：US09436901

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/173

CPC classification number: G06F12/0831 ,  G06F12/0813

Abstract: A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier. In response to receipt of the write data transaction, the destination logic transmits the write data transaction to a next segment only if the destination identifier does not match a node identifier associated with a node containing a current segment.

Abstract translation: 数据处理系统包括多个节点，每个节点包含至少一个代理，并且每个节点都具有相关联的节点标识符，以及分布在多个节点之间的存储器。 数据处理系统还包括一个包含分段数据信道的互连，其中每个节点包含分段数据信道的一个段，并且每个段通过目的地逻辑耦合到至少一个其它段。 响应于在互连上窥探主代理的写请求，将服务于写请求的目标代理将其节点标识符置于窥探响应中。 当主代理接收到包含目标代理的节点标识符的组合响应时，主代理在分段数据信道上发出指定目标代理的节点标识符的写数据事务作为目的地标识符。 响应于写入数据事务的接收，目的地逻辑仅在目的地标识符与与包含当前段的节点相关联的节点标识符不匹配时才将写入数据事务发送到下一个段。