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公开(公告)号：US10264353B2
公开(公告)日：2019-04-16
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US10168363B1
公开(公告)日：2019-01-01
申请号：US15920896
申请日：2018-03-14
Inventor： Sandor Petenyi
Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.
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公开(公告)号：US09823965B2
公开(公告)日：2017-11-21
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Di Stefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
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14.发明申请公开(公告)号：US20170194855A1
公开(公告)日：2017-07-06
申请号：US14986425
申请日：2015-12-31
Inventor： Sandor Petenyi
CPC classification number: G05F1/625
Abstract: A voltage regulator is controlled to improve supply voltage rejection by cancelling an alternating component of a supply voltage signal that is capacitively coupled to a high-impedance node within the voltage regulator. This cancellation is done by capacitively coupling an inverted version of the alternating component to the high-impedance node to thereby substantially cancel the alternating component present on the high-impedance node. The high-impedance node may be a high-impedance voltage reference node of the voltage regulator.
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公开(公告)号：US09645594B2
公开(公告)日：2017-05-09
申请号：US14881498
申请日：2015-10-13
Inventor： Sandor Petenyi
CPC classification number: G05F1/575
Abstract: A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage. The driver includes an impedance device, and a driver transistor that receives the drive signal so as to vary a bias current to a control terminal of the power transistor. The dropout detector and the bias current limiter is coupled to the input terminal, the impedance device, and the output terminal and includes first and second transistors coupled together, and a bias current generator coupled to the second transistor.
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Patent Agency Ranking
公开(公告)号：US12088429B2
公开(公告)日：2024-09-10
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , H03K7/08 , H04L12/40
CPC classification number: H04L12/403 , H03K7/08 , H04L12/40006 , H04L2012/40215
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US20230300001A1
公开(公告)日：2023-09-21
申请号：US18174387
申请日：2023-02-24
Applicant: STMicroelectronics Application GMBH , STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. , STMicroelectronics S.r.l.
Inventor： Fred Rennig , Jochen Barthel , Ludek Beran , Mirko Dondini , Vaclav Dvorak , Vincenzo Polisi , Marianna Sanza' , CalogeroAndrea Trecarichi , Alfonso Furio
IPC: H04L12/40 , H03K19/00 , H03K17/687
CPC classification number: H04L12/40169 , H03K19/0002 , H03K17/6872 , H03K17/6874 , H04L12/40032 , H04L2012/40273 , H04L2012/40215
Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
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公开(公告)号：US11652457B2
公开(公告)日：2023-05-16
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor Petenyi
CPC classification number: H03F3/45179 , H03F1/0205 , H03F1/301 , H03F2200/78 , H03F2203/45
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
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公开(公告)号：US11526458B2
公开(公告)日：2022-12-13
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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公开(公告)号：US20220159807A1
公开(公告)日：2022-05-19
申请号：US17523641
申请日：2021-11-10
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics Design and Application S.R.O.
Inventor： Donato TAGLIAVIA , Vincenzo POLISI , Calogero Andrea TRECARICHI , Francesco Nino MAMMOLITI , Jochen BARTHEL , Ludek BERAN
Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.
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